On Tue, Jul 15, 2025 at 07:51:03PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > Testing > ------- > > I've lost access to my test setup now. So Krishna (Cced) will help with > testing > on the Qcom platform and Wilfred or Niklas should be able to test it on > Rockchip > platform. For the moment, this series is compile tested only.
Since this patch series implements two things: 1) Testing sysfs initiated reset: selftests before sysfs initiated reset: # FAILED: 14 / 16 tests passed. # echo 1 > /sys/bus/pci/devices/0000:01:00.0/reset [ 145.567748] pci-endpoint-test 0000:01:00.0: resetting [ 145.638755] rockchip-dw-pcie a40000000.pcie: PCIE_CLIENT_INTR_STATUS_MISC: 0x3 [ 145.639472] rockchip-dw-pcie a40000000.pcie: LTSSM_STATUS: 0x230011 [ 145.640063] rockchip-dw-pcie a40000000.pcie: Received Link up event. Starting enumeration! [ 145.682612] rockchip-dw-pcie a40000000.pcie: PCIe Gen.3 x4 link up [ 145.683162] rockchip-dw-pcie a40000000.pcie: Root Port reset completed [ 145.810852] pci-endpoint-test 0000:01:00.0: reset done selftests after sysfs initiated reset: # FAILED: 14 / 16 tests passed. (Without this patch series: # FAILED: 7 / 16 tests passed.) So for this part: Tested-by: Niklas Cassel <cas...@kernel.org> 2) Testing link down reset: selftests before link down reset: # FAILED: 14 / 16 tests passed. ## On EP side: # echo 0 > /sys/kernel/config/pci_ep/controllers/a40000000.pcie-ep/start && \ sleep 0.1 && echo 1 > /sys/kernel/config/pci_ep/controllers/a40000000.pcie-ep/start [ 111.137162] rockchip-dw-pcie a40000000.pcie: PCIE_CLIENT_INTR_STATUS_MISC: 0x4 [ 111.137881] rockchip-dw-pcie a40000000.pcie: LTSSM_STATUS: 0x0 [ 111.138432] rockchip-dw-pcie a40000000.pcie: hot reset or link-down reset [ 111.139067] pcieport 0000:00:00.0: Recovering Root Port due to Link Down [ 111.139686] pci-endpoint-test 0000:01:00.0: AER: can't recover (no error_detected callback) [ 111.255407] rockchip-dw-pcie a40000000.pcie: PCIe Gen.3 x4 link up [ 111.256019] rockchip-dw-pcie a40000000.pcie: Root Port reset completed [ 111.383401] pcieport 0000:00:00.0: Root Port has been reset [ 111.384060] pcieport 0000:00:00.0: AER: device recovery failed [ 111.384582] rockchip-dw-pcie a40000000.pcie: PCIE_CLIENT_INTR_STATUS_MISC: 0x3 [ 111.385218] rockchip-dw-pcie a40000000.pcie: LTSSM_STATUS: 0x230011 [ 111.385771] rockchip-dw-pcie a40000000.pcie: Received Link up event. Starting enumeration! [ 111.390866] pcieport 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 111.391650] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 Basically all tests timeout # FAILED: 1 / 16 tests passed. Which is the same as before this patch series. So AFAICT, this part does not seem to work as advertised. Instead of quickly stopping and starting the link, I also tried to reboot the EP board, which does the configfs writes and starts the link automatically on boot, but that had the same result as quickly stopping and starting the link. Kind regards, Niklas
