On Fri, Jun 20, 2014 at 3:04 AM, Thomas Gleixner <t...@linutronix.de> wrote:
> None of the chips has a ACK register.
I need to recheck on this after looking at datasheets. Arranging for
them, will revert by tomorrow.
> The code brainlessly fiddles
> with the enable register, so it might even reenable a disabled
> interrupt at least on spear300.
Ack/Clear register is only configured for SPEAr320, how will it
make a difference to SPEAr300 ?
And for SPEAr320 as well, the offset mentioned in code for clear
register is different then ENABLE register.
> Index: linux/drivers/irqchip/spear-shirq.c
> ===================================================================
> --- linux.orig/drivers/irqchip/spear-shirq.c
> +++ linux/drivers/irqchip/spear-shirq.c
> @@ -33,15 +33,11 @@
> * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
> * status_reg: status register offset
> * status_reg_mask: status register valid mask
> - * clear_reg: clear register offset
> - * reset_to_clear: val 1 indicates, we need to clear bit for clearing
> interrupt
> */
> struct shirq_regs {
> u32 enb_reg;
> u32 reset_to_enb;
> u32 status_reg;
> - u32 clear_reg;
> - u32 reset_to_clear;
AFAIR, there was a revision for SPEAr320 which was actually using
reset_to_clear and so was present in code. But later revisions got rid
of it and code never got updated.
> @@ -150,13 +141,6 @@ static struct spear_shirq spear320_shirq
> .nr_irqs = 7,
> .mask = ((0x1 << 7) - 1) << 0,
> .disabled = 1,
> - .regs = {
> - .enb_reg = SPEAR320_INT_ENB_MASK_REG,
> - .reset_to_enb = 1,
> - .status_reg = SPEAR320_INT_STS_MASK_REG,
> - .clear_reg = SPEAR320_INT_CLR_MASK_REG,
> - .reset_to_clear = 1,
> - },
Was removing .regs completely intentional?
I don't see these registers getting added again in later patches.
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