Order the ras blocks in the order of interrupts not alphabetically.

Signed-off-by: Thomas Gleixner <t...@linutronix.de>
---
 drivers/irqchip/spear-shirq.c |   26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

Index: linux/drivers/irqchip/spear-shirq.c
===================================================================
--- linux.orig/drivers/irqchip/spear-shirq.c
+++ linux/drivers/irqchip/spear-shirq.c
@@ -138,20 +138,22 @@ static struct spear_shirq *spear310_shir
 #define SPEAR320_INT_CLR_MASK_REG              0x04
 #define SPEAR320_INT_ENB_MASK_REG              0x08
 
-static struct spear_shirq spear320_shirq_ras1 = {
-       .offset         = 7,
-       .nr_irqs        = 3,
+static struct spear_shirq spear320_shirq_ras3 = {
+       .offset         = 0,
+       .nr_irqs        = 7,
+       .disabled       = 1,
        .regs = {
-               .enb_reg = -1,
+               .enb_reg = SPEAR320_INT_ENB_MASK_REG,
+               .reset_to_enb = 1,
                .status_reg = SPEAR320_INT_STS_MASK_REG,
                .clear_reg = SPEAR320_INT_CLR_MASK_REG,
                .reset_to_clear = 1,
        },
 };
 
-static struct spear_shirq spear320_shirq_ras2 = {
-       .offset         = 10,
-       .nr_irqs        = 1,
+static struct spear_shirq spear320_shirq_ras1 = {
+       .offset         = 7,
+       .nr_irqs        = 3,
        .regs = {
                .enb_reg = -1,
                .status_reg = SPEAR320_INT_STS_MASK_REG,
@@ -160,13 +162,11 @@ static struct spear_shirq spear320_shirq
        },
 };
 
-static struct spear_shirq spear320_shirq_ras3 = {
-       .offset         = 0,
-       .nr_irqs        = 7,
-       .disabled       = 1,
+static struct spear_shirq spear320_shirq_ras2 = {
+       .offset         = 10,
+       .nr_irqs        = 1,
        .regs = {
-               .enb_reg = SPEAR320_INT_ENB_MASK_REG,
-               .reset_to_enb = 1,
+               .enb_reg = -1,
                .status_reg = SPEAR320_INT_STS_MASK_REG,
                .clear_reg = SPEAR320_INT_CLR_MASK_REG,
                .reset_to_clear = 1,


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