On Fri, 20 Jun 2014, Viresh Kumar wrote:
> On Fri, Jun 20, 2014 at 3:04 AM, Thomas Gleixner <t...@linutronix.de> wrote:
>
> > Index: linux/drivers/irqchip/spear-shirq.c
> > -struct shirq_regs {
> > - u32 enb_reg;
> > - u32 reset_to_enb;
>
> I don't see something similar to 'reset_to_enb' is added again.
> AFAICT, this field is being used by two blocks:
>
> spear300_shirq_ras1: writes 0 to this. i.e. we need to write 0 to
> mask the interrupt
>
> and
>
> spear320_shirq_ras3: writes 1 to this. i.e. we need to write 1 to
> mask the interrupt.
AGAIN: spear320_shirq_ras3 is never instantiated as a chained irq. So
the chip for these interrupts is never set.
And if it ever is, you need a separate irq chip for it and not some
conditional hackery.
> And so the new code you have added breaks it for SPEAr300 ?
+static void shirq_irq_mask(struct irq_data *d)
+{
+ struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
+ u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
+ u32 __iomem *reg = shirq->base + shirq->regs.enb_reg;
+
+ raw_spin_lock(&shirq_lock);
+ val = readl(reg) & ~(0x1 << shift);
+ writel(val, reg);
+ raw_spin_unlock(&shirq_lock);
+}
That's the mask function for 300 and it clears the bit, right?
Thanks,
tglx
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