On Sat, Sep 09, 2017 at 09:11:33PM +0200, Borislav Petkov wrote:
> On Sat, Sep 09, 2017 at 08:46:38PM +0200, Markus Trippelsdorf wrote:
> > OK. ADDR is 12. The rest is the same (modulo time).
>
> I'm assuming that's 12 hex... yeah, "ADDR %llx ".
>
> Dammit, that should have "0x" prepended. Grrr, I'll fix all that next
> week.
Ok, that 0x12 looks like it fits the TlbCacheDis thing (bits [5:1]):
"0_1001b
Link: A specific coherent-only packet from a CPU was issued to an
IO link. This may be caused by software which addresses page table
structures in a memory type other than cacheable WB-DRAM without
properly configuring MSRC001_0015[TlbCacheDis]. This may occur, for
example, when page table structure addresses are above top of memory. In
such cases, the NB will generate an MCE if it sees a mismatch between
the memory operation generated by the core and the link type. See
2.9.3.1.2 [Determining The Access Destination for CPU Accesses]."
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
