On Sat, Sep 9, 2017 at 11:14 AM, Markus Trippelsdorf
<mar...@trippelsdorf.de> wrote:
>
> I think the issue gets fixed by:
>
> # wrmsr -a 0xc0010015 0x1000018
>
> Setting bit 3 of the Hardware Configuration Register to 1.
>
> Quote for the docs:
> »TlbCacheDis: cacheable memory disable. Read-write. 0=Enables performance
> optimization that
> assumes PML4, PDP, PDE, and PTE entries are in cacheable WB-DRAM
Uhhuh.
The page directories should *definitely* always be in cacheable
memory, so it should be ok for that bit to be 0, and it's possible
that setting it to 1 will seriously screw up performance.
But the fact that that fixes it for you does indicate that it's not
just a stale TLB entry or something, it really is some CPU using page
tables after they have been free'd and been re-allocated to something
else (and *then* they may point to garbage).
So I do think it's a sign that we definitely need that IPI for you.
Linus
