On 2017.09.09 at 19:36 +0200, Borislav Petkov wrote: > On Sat, Sep 09, 2017 at 07:23:52PM +0200, Markus Trippelsdorf wrote: > > Hmm, the output is exactly the same as before your patch. > > Bah, that patch doesn't account for the fact that we're rereading the > status field again in do_machine_check(). > > Ok, let's force MCi_ADDR out. Ontop:
Thanks, will try it later. I think the issue gets fixed by: # wrmsr -a 0xc0010015 0x1000018 Setting bit 3 of the Hardware Configuration Register to 1. Quote for the docs: »TlbCacheDis: cacheable memory disable. Read-write. 0=Enables performance optimization that assumes PML4, PDP, PDE, and PTE entries are in cacheable WB-DRAM; memory type checks may be bypassed, and addresses outside of WB-DRAM may result in undefined behavior or NB protocol errors. 1=Disables performance optimization and allows PML4, PDP, PDE and PTE entries to be in any memory type. Operating systems that maintain page tables in memory types other than WB- DRAM must set TlbCacheDis to insure proper operation.« I've been successfully compiling for over 15 minutes now. -- Markus
