On 5/29/2015 10:51 PM, Daniel Vetter wrote:
On Fri, May 29, 2015 at 04:07:03PM +0530, Gaurav K Singh wrote:
During enable sequence for MIPI encoder in command mode, enable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
Signed-off-by: Gaurav K Singh <gaurav.k.si...@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimu...@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.ku...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index cab2ac8..fc84313 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -44,6 +44,7 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_rect.h>
#include <linux/dma_remapping.h>
+#include "intel_dsi.h"
/* Primary plane formats supported by all gen */
#define COMMON_PRIMARY_FORMATS \
@@ -2110,6 +2111,8 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *encoder;
+ struct intel_dsi *intel_dsi;
enum pipe pipe = crtc->pipe;
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
pipe);
@@ -2154,6 +2157,18 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
return;
}
+ for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
+ if (encoder->type == INTEL_OUTPUT_DSI) {
+ intel_dsi = enc_to_intel_dsi(&encoder->base);
+ if (intel_dsi && (intel_dsi->operation_mode ==
+ INTEL_DSI_COMMAND_MODE)) {
+ val = val | PIPECONF_MIPI_DSR_ENABLE;
+ I915_WRITE(reg, val);
+ }
+ break;
+ }
+ }
When we have these kind of encoder/crtc state depencies we resolve them by
adding a bit of state to intel_crtc_state which is set as needed in the
encoder's compute_config callback. Then all you need here is
if (intel_state->dsi_self_refresh)
val |= PIPECONF_MIPI_DSR_ENABLE;
Also is that additional write really required?
-Daniel
Yes additional write is required. MIPI_DSR_ENABLE has to be written
first then followed
by pipe enable. if MIPI_DSR_ENABLE and pipe enable is done in same
write, observed
that the image from pipe is not sent to panel when issued mem write command.
Having a state variable instead of looping through the encoders
definitely looks good.
Need to find a place to update the state variable. I will get back on this.
+
I915_WRITE(reg, val | PIPECONF_ENABLE);
POSTING_READ(reg);
}
--
1.7.9.5
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