On Wed, May 31, 2006 at 10:49:35PM +0200, Wolfgang Mües wrote: > > (define_insn "*arm_movqi_insn" > > [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,Q") > > (match_operand:QI 1 "general_operand" "rI,K,m,+r"))] > > "TARGET_ARM > > && ( register_operand (operands[0], QImode) > > > > || register_operand (operands[1], QImode))" > > > > "@ > > mov%?\\t%0, %1 > > mvn%?\\t%0, #%B1 > > ldr%?b\\t%0, %1 > > swp%?b\\t%1, %1, [%M0]" > > [(set_attr "type" "*,*,load1,store1") > > (set_attr "predicable" "yes")] > > ) > > Changing "m" to "Q", narrowing the address modes > Changing "r" to "+r", (register is globbered) > and of course making the swpb call..
I think you will need to remove the '+' as already suggested and add (clobber (match_scratch:QI "=X,X,X,1")) to tell GCC that the register allocated to operand 1 is clobbered by the instruction for this particular alternative. You will also have to modify any code which expands this pattern accordingly. -- Rask Ingemann Lambertsen
