Paul, thank you for commenting...
On Tuesday 30 May 2006 22:03, Paul Brook wrote: > > I found arm.md and the moveqi insns, but because of the different > > addressing modes of strb and swpb, its not easy to make the change. > > And there must be a compiler option for this, too. > > > > Could somebody please tell me how to implement this change? > > Short answer is probably not. > > There are a couple of complications that spring to mind. The > different addressing modes and the fact that swp clobbers a register > are the most immediate ones. > > You'll need to modify at least the movqi insn patterns, memory > constraints and the legitimate address stuff. I'm not sure about the > clobber, that might need additional reload-related machinery. For the first shot, I have changed > (define_insn "*arm_movqi_insn" > [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") > (match_operand:QI 1 "general_operand" "rI,K,m,r"))] > "TARGET_ARM > && ( register_operand (operands[0], QImode) > > || register_operand (operands[1], QImode))" > > "@ > mov%?\\t%0, %1 > mvn%?\\t%0, #%B1 > ldr%?b\\t%0, %1 > str%?b\\t%1, %0" > [(set_attr "type" "*,*,load1,store1") > (set_attr "predicable" "yes")] > ) into > (define_insn "*arm_movqi_insn" > [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,Q") > (match_operand:QI 1 "general_operand" "rI,K,m,+r"))] > "TARGET_ARM > && ( register_operand (operands[0], QImode) > > || register_operand (operands[1], QImode))" > > "@ > mov%?\\t%0, %1 > mvn%?\\t%0, #%B1 > ldr%?b\\t%0, %1 > swp%?b\\t%1, %1, [%M0]" > [(set_attr "type" "*,*,load1,store1") > (set_attr "predicable" "yes")] > ) Changing "m" to "Q", narrowing the address modes Changing "r" to "+r", (register is globbered) and of course making the swpb call.. Gcc compiles, but does a segfault while compiling ARM programs. regards Wolfgang -- We're back to the times when men were men and wrote their own device drivers. (Linus Torvalds)
