Spec:
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett <mary.benn...@embecosm.com>
Nandni Jamnadas <nandni.jamna...@embecosm.com>
Pietra Ferreira <pietra.ferre...@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackm...@embecosm.com>
Simon Cook <simon.c...@embecosm.com>
Jeremy Bennett <jeremy.benn...@embecosm.com>
Helene Chelin <helene.che...@embecosm.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVelw.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVelw builtin documentation.
* doc/sourcebuild.texi: Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw.
* testsuite/lib/target-supports.exp: Add proc for the XCVelw extension.
---
gcc/common/config/riscv/riscv-common.cc | 2 ++
gcc/config/riscv/corev.def | 3 +++
gcc/config/riscv/corev.md | 15 +++++++++++++++
gcc/config/riscv/riscv-builtins.cc | 2 ++
gcc/config/riscv/riscv-ftypes.def | 1 +
gcc/config/riscv/riscv.opt | 2 ++
gcc/doc/extend.texi | 8 ++++++++
gcc/doc/sourcebuild.texi | 3 +++
.../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++++++++
gcc/testsuite/lib/target-supports.exp | 13 +++++++++++++
10 files changed, 60 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 526dbb7603b..6a1978bd0e4 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -312,6 +312,7 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1667,6 +1668,7 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
{"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
+ {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
{"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
{"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def
index 17580df3c41..3b9ec029d06 100644
--- a/gcc/config/riscv/corev.def
+++ b/gcc/config/riscv/corev.def
@@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN",
RISCV_BUILTIN_DIRECT, RISCV_SI_FT
RISCV_BUILTIN (cv_alu_subuN, "cv_alu_subuN", RISCV_BUILTIN_DIRECT,
RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
RISCV_BUILTIN (cv_alu_subRN, "cv_alu_subRN", RISCV_BUILTIN_DIRECT,
RISCV_SI_FTYPE_SI_SI_UQI, cvalu),
RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT,
RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
+
+// XCVELW
+RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT,
RISCV_USI_FTYPE_VOID_PTR, cvelw),
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 1350bd4b81e..c7a2ba07bcc 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -24,6 +24,9 @@
UNSPEC_CV_ALU_CLIPR
UNSPEC_CV_ALU_CLIPU
UNSPEC_CV_ALU_CLIPUR
+
+ ;;CORE-V EVENT LOAD
+ UNSPECV_CV_ELW
])
;; XCVMAC extension.
@@ -691,3 +694,15 @@
cv.suburnr\t%0,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
+
+;; XCVELW builtins
+(define_insn "riscv_cv_elw_elw_si"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile [(match_operand:SI 1 "move_operand" "p")]
+ UNSPECV_CV_ELW))]
+
+ "TARGET_XCVELW && !TARGET_64BIT"
+ "cv.elw\t%0,%a1"
+
+ [(set_attr "type" "load")
+ (set_attr "mode" "SI")])
diff --git a/gcc/config/riscv/riscv-builtins.cc
b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..5ee11ebe3bc 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0))
// CORE-V AVAIL
AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
+AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
/* Construct a riscv_builtin_description from the given arguments.
@@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
#define RISCV_ATYPE_HI intHI_type_node
#define RISCV_ATYPE_SI intSI_type_node
#define RISCV_ATYPE_VOID_PTR ptr_type_node
+#define RISCV_ATYPE_INT_PTR integer_ptr_type_node
/* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs. */
diff --git a/gcc/config/riscv/riscv-ftypes.def
b/gcc/config/riscv/riscv-ftypes.def
index 0d1e4dd061e..3e7d5c69503 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -30,6 +30,7 @@ DEF_RISCV_FTYPE (0, (USI))
DEF_RISCV_FTYPE (0, (VOID))
DEF_RISCV_FTYPE (1, (VOID, USI))
DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
+DEF_RISCV_FTYPE (1, (USI, VOID_PTR))
DEF_RISCV_FTYPE (1, (USI, USI))
DEF_RISCV_FTYPE (1, (UDI, UDI))
DEF_RISCV_FTYPE (1, (USI, UQI))
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 70d78151cee..0eac6d44fae 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -411,6 +411,8 @@ Mask(XCVMAC) Var(riscv_xcv_subext)
Mask(XCVALU) Var(riscv_xcv_subext)
+Mask(XCVELW) Var(riscv_xcv_subext)
+
TargetVariable
int riscv_xthead_subext
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index c8fc4e391b5..b890acccac1 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21970,6 +21970,14 @@ Generated assembler @code{cv.subuRN} if the uint8_t
operand is a constant and in
Generated assembler @code{cv.subuRNr} if the it is a register.
@end deftypefn
+These built-in functions are available for the CORE-V Event Load machine
+architecture. For more information on CORE-V ELW builtins, please see
+@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-event-load-word-builtins-xcvelw}
+
+@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_elw_elw (uint32_t
*)
+Generated assembler @code{cv.elw}
+@end deftypefn
+
@node RX Built-in Functions
@subsection RX Built-in Functions
GCC supports some of the RX instructions which cannot be expressed in
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index c20af31c642..06a6d1776ff 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2481,6 +2481,9 @@ Test system has support for the CORE-V MAC extension.
@item cv_alu
Test system has support for the CORE-V ALU extension.
+@item cv_elw
+Test system has support for the CORE-V ELW extension.
+
@end table
@subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
new file mode 100644
index 00000000000..30f951c3f0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_elw } */
+/* { dg-options "-march=rv32i_xcvelw -mabi=ilp32" } */
+
+int
+foo (void* b)
+{
+ return __builtin_riscv_cv_elw_elw (b + 8);
+}
+
+/* { dg-final { scan-assembler-times
"cv\\.elw\t\[a-z\]\[0-99\],\[0-99\]\\(\[a-z\]\[0-99\]\\)" 1 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 024939ee2e7..f388360ae56 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13085,6 +13085,19 @@ proc check_effective_target_cv_alu { } {
} "-march=rv32i_xcvalu" ]
}
+# Return 1 if the CORE-V ELW extension is available.
+proc check_effective_target_cv_elw { } {
+ if { !([istarget riscv*-*-*]) } {
+ return 0
+ }
+ return [check_no_compiler_messages cv_elw object {
+ void foo (void)
+ {
+ asm ("cv.elw x0, 0(x0)");
+ }
+ } "-march=rv32i_xcvelw" ]
+}
+
proc check_effective_target_loongarch_sx { } {
return [check_no_compiler_messages loongarch_lsx assembly {
#if !defined(__loongarch_sx)
--
2.34.1
