On 11/8/23 04:09, Mary Bennett wrote:
+;; XCVELW builtins
+(define_insn "riscv_cv_elw_elw_si"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
+ UNSPECV_CV_ELW))]
+
+ "TARGET_XCVELW && !TARGET_64BIT"
+ "cv.elw\t%0,%a1"
+
+ [(set_attr "type" "load")
+ (set_attr "mode" "SI")])
Would it make more sense to pull the MEM into the operand? So instead
of "address_operand", you'd define a new operand predicate which
accepted (mem (...)) and that chunk of your insn looks like
(unspec_volatile [(match_operand:SI 1 "new_predicate" "")] UNSPEC_CV_ELW))]
Or something close to that.
From a quick look at the docs it looks like the addressing modes are
similar to other extensions and could be re-used.
Thoughts?
jeff
