On 11/8/23 04:09, Mary Bennett wrote:
Spec:
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett <mary.benn...@embecosm.com>
Nandni Jamnadas <nandni.jamna...@embecosm.com>
Pietra Ferreira <pietra.ferre...@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackm...@embecosm.com>
Simon Cook <simon.c...@embecosm.com>
Jeremy Bennett <jeremy.benn...@embecosm.com>
Helene Chelin <helene.che...@embecosm.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch<mode> pattern
for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Change pattern priority so corev.md
patterns run before riscv.md patterns.
* config/riscv/constraints.md: Implement constraints
cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 0109e1836cf..7d7b952d817 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,17 @@
[(set_attr "type" "load")
(set_attr "mode" "SI")])
+
+;; XCVBI Builtins
+(define_insn "cv_branch<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "equality_operator"
+ [(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand"
"CV_bi_sign5")])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_XCVBI"
+ "cv.b%C1imm\t%2,%3,%0"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
Note that technically you could use "i" or "n" for the constraint of
operand 3. This works because the predicate has priority and it only
allows -16..15.
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index ae2217d0907..168c8665a7a 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -579,6 +579,14 @@
(define_asm_attributes
[(set_attr "type" "multi")])
+;; ..............................
+;;
+;; Machine Description Patterns
+;;
+;; ..............................
+
+(include "corev.md")
I would put a comment here indicating why a subtarget might want to
include its patterns before the standard patterns in riscv.md.
OK with the comment added. Your decision on whether or not to drop the
CV_bi_sign5 constraint and replace it with "n".
Jeff
