Re: [PATCH] rs6000, vector integer multiply/divide/modulo instructions

[Pat Haugen via Gcc-patches]

On 11/4/20 10:44 AM, Carl Love via Gcc-patches wrote:
> +
> +(define_insn "vdives_<mode>"
> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +        (unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v")
> +                     (match_operand:VIlong 2 "vsx_register_operand" "v")]
> +                    UNSPEC_VDIVES))]
> +  "TARGET_POWER10"
> +  "vdives<VIlong_char> %0,%1,%2"
> +  [(set_attr "type" "vecsimple")])
> +
> +(define_insn "vdiveu_<mode>"
> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +        (unspec: VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v")
> +                      (match_operand:VIlong 2 "vsx_register_operand" "v")]
> +                     UNSPEC_VDIVEU))]
> +  "TARGET_POWER10"
> +  "vdiveu<VIlong_char> %0,%1,%2"
> +  [(set_attr "type" "vecsimple")])
> +
> +(define_insn "div<mode>3"
> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +     (div:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v")
> +                 (match_operand:VIlong 2 "vsx_register_operand" "v")))]
> +  "TARGET_POWER10"
> +  "vdivs<VIlong_char> %0,%1,%2"
> +  [(set_attr "type" "vecsimple")])
> +
> +(define_insn "udiv<mode>3"
> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +     (udiv:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v")
> +                 (match_operand:VIlong 2 "vsx_register_operand" "v")))]
> +  "TARGET_POWER10"
> +  "vdivu<VIlong_char> %0,%1,%2"
> +  [(set_attr "type" "vecsimple")])
> +
> +(define_insn "vmods_<mode>"
> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +     (mod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v")
> +                 (match_operand:VIlong 2 "vsx_register_operand" "v")))]
> +  "TARGET_POWER10"
> +  "vmods<VIlong_char> %0,%1,%2"
> +  [(set_attr "type" "vecsimple")])
> +
> +(define_insn "vmodu_<mode>"
> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +     (umod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v")
> +                  (match_operand:VIlong 2 "vsx_register_operand" "v")))]
> +  "TARGET_POWER10"
> +  "vmodu<VIlong_char> %0,%1,%2"
> +  [(set_attr "type" "vecsimple")])

Since the vdiv.../vmod... instructions execute in the fixed point divide unit, 
all the above instructions should have a type of "div" instead of "vecsimple".


> +
> +(define_insn "vmulhs_<mode>"
> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +     (unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v")
> +                     (match_operand:VIlong 2 "vsx_register_operand" "v")]
> +                    UNSPEC_VMULHS))]
> +  "TARGET_POWER10"
> +  "vmulhs<VIlong_char> %0,%1,%2"
> +  [(set_attr "type" "vecsimple")])
> +
> +(define_insn "vmulhu_<mode>"
> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> +     (unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v")
> +                     (match_operand:VIlong 2 "vsx_register_operand" "v")]
> +                    UNSPEC_VMULHU))]
> +  "TARGET_POWER10"
> +  "vmulhu<VIlong_char> %0,%1,%2"
> +  [(set_attr "type" "vecsimple")])> +
> +;; Vector multiply low double word
> +(define_insn "mulv2di3"
> +  [(set (match_operand:V2DI 0 "vsx_register_operand" "=v")
> +     (mult:V2DI (match_operand:V2DI 1 "vsx_register_operand" "v")
> +                (match_operand:V2DI 2 "vsx_register_operand" "v")))]
> +  "TARGET_POWER10"
> +  "vmulld %0,%1,%2"
> +  [(set_attr "type" "vecsimple")])

Similarly, the above 3 insns should have a "mul" instruction type.

-Pat