On Tue, Nov 24, 2020 at 08:34:51PM -0600, Pat Haugen wrote:
> On 11/24/20 8:17 PM, Pat Haugen via Gcc-patches wrote:
> > On 11/24/20 12:59 PM, Carl Love via Gcc-patches wrote:
> >> +(define_insn "modu_<mode>"
> >> + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
> >> + (umod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v")
> >> + (match_operand:VIlong 2 "vsx_register_operand" "v")))]
> >> + "TARGET_POWER10"
> >> + "vmodu<wd> %0,%1,%2"
> >> + [(set_attr "type" "vecdiv")
> >> + (set_attr "size" "128")])
> >
> > We should only be setting "size" "128" for instructions that operate on
> > scalar 128-bit data items (i.e. 'vdivesq' etc). Since the above insns are
> > either V2DI/V4SI (ala VIlong mode_iterator), they shouldn't be marked as
> > size 128. If you want to set the size based on mode, (set_attr "size"
> > "<bits>") should do the trick I believe.
>
> Well, after you update "(define_mode_attr bits" in rs6000.md for V2DI/V4SI.
So far, <size> was only used for scalars. I agree that for vectors it
makes most sense to do the element size (because the vector size always
is 128 bits, and for scheduling the element size can matter). But, the
definitions of <size> and <bits> now say
;; What data size does this instruction work on?
;; This is used for insert, mul and others as necessary.
(define_attr "size" "8,16,32,64,128" (const_string "32"))
and
;; How many bits in this mode?
(define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")
(SF "32") (DF "64")])
so those need a bit of update as well then :-)
Segher
