This patch eliminates TARGET_UPPER_REGS_DI. I deleted the poison attribute in
patch #1. I will combine the ChangeLog and submit this patch and the previous
patch together if approved.
It bootstraps and has no regressions on big endian power7 and little endian
power8. Can I install this patch on the trunk.
2017-07-25 Michael Meissner <meiss...@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_option_override_internal):
Eliminate TARGET_UPPER_REGS_DI.
(rs6000_expand_vector_set): Likewise.
* config/rs6000/vsx.md (vsx_set_<mode>_p9): Likewise.
(vsx_set_v4sf_p9): Likewise.
(vsx_set_v4sf_p9_zero): Likewise.
(vsx_insert_extract_v4sf_p9): Likewise.
(vsx_insert_extract_v4sf_p9_2): Likewise.
* config/rs6000/rs6000.c (TARGET_UPPER_REGS_DI): Delete.
(TARGET_VEXTRACTUB): Eliminate TARGET_UPPER_REGS_DI.
(TARGET_DIRECT_MOVE_64BIT): Likewise.
* config/rs6000/rs6000.md
(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(Splitters for DI constants in Altivec registers): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 250487)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -4637,11 +4637,11 @@ rs6000_option_override_internal (bool gl
variables through memory to do moves. SImode can be used on ISA 2.07,
while HImode and QImode require ISA 3.0. */
if (TARGET_VSX_SMALL_INTEGER
- && (!TARGET_DIRECT_MOVE || !TARGET_P8_VECTOR || !TARGET_UPPER_REGS_DI))
+ && (!TARGET_DIRECT_MOVE || !TARGET_P8_VECTOR))
{
if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_SMALL_INTEGER)
error ("-mvsx-small-integer requires -mpower8-vector, "
- "-mupper-regs-di, and -mdirect-move");
+ "and -mdirect-move");
rs6000_isa_flags &= ~OPTION_MASK_VSX_SMALL_INTEGER;
}
@@ -7338,8 +7338,7 @@ rs6000_expand_vector_set (rtx target, rt
else if (mode == V2DImode)
insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
- else if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
+ else if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER &&
TARGET_POWERPC64)
{
if (mode == V4SImode)
insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md (revision 250485)
+++ gcc/config/rs6000/vsx.md (working copy)
@@ -3366,7 +3366,7 @@ (define_insn "vsx_set_<mode>_p9"
(match_operand:QI 3 "<VSX_EXTRACT_PREDICATE>" "n")]
UNSPEC_VSX_SET))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_P9_VECTOR &&
TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
+ && TARGET_POWERPC64"
{
int ele = INTVAL (operands[3]);
int nunits = GET_MODE_NUNITS (<MODE>mode);
@@ -3391,7 +3391,7 @@ (define_insn_and_split "vsx_set_v4sf_p9"
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
+ && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 5)
@@ -3427,7 +3427,7 @@ (define_insn_and_split "*vsx_set_v4sf_p9
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
+ && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 4)
@@ -3458,7 +3458,7 @@ (define_insn "*vsx_insert_extract_v4sf_p
(match_operand:QI 4 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64
+ && TARGET_POWERPC64
&& (INTVAL (operands[3]) == (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
{
int ele = INTVAL (operands[4]);
@@ -3486,8 +3486,7 @@ (define_insn_and_split "*vsx_insert_extr
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 5 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode)
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64
+ && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64
&& (INTVAL (operands[3]) != (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
"#"
"&& 1"
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (revision 250487)
+++ gcc/config/rs6000/rs6000.h (working copy)
@@ -571,16 +571,6 @@ extern int rs6000_vector_align[];
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
-/* We previously had -mupper-regs-{df,di,sf} to control whether DFmode, DImode,
- and/or SFmode could go in the traditional Altivec registers. GCC 8.x
deleted
- these options. In order to simplify the code, define the options in terms
- of the base option (vsx, power8-vector). */
-#if (GCC_VERSION >= 3000)
-#pragma GCC poison TARGET_UPPER_REGS_DF TARGET_UPPER_REGS_SF
-#endif
-
-#define TARGET_UPPER_REGS_DI TARGET_VSX
-
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or
XILINX. */
@@ -610,7 +600,7 @@ extern int rs6000_vector_align[];
#define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
&& TARGET_POWERPC64)
#define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
+ && TARGET_POWERPC64)
/* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
#define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
@@ -770,7 +760,6 @@ extern int rs6000_vector_align[];
#define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
&& TARGET_P8_VECTOR \
&& TARGET_POWERPC64 \
- && TARGET_UPPER_REGS_DI \
&& (rs6000_altivec_element_order != 2))
/* Whether the various reciprocal divide/square root estimate instructions
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 250487)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -5438,7 +5438,7 @@ (define_insn_and_split "*float<QHI:mode>
(clobber (match_scratch:DI 3 "=X,r,X"))
(clobber (match_scratch:<QHI:MODE> 4 "=X,X,wK"))]
"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_UPPER_REGS_DI && TARGET_VSX_SMALL_INTEGER"
+ && TARGET_VSX_SMALL_INTEGER"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -8664,7 +8664,7 @@ (define_split
(define_split
[(set (match_operand:DI 0 "altivec_register_operand" "")
(match_operand:DI 1 "s5bit_cint_operand" ""))]
- "TARGET_UPPER_REGS_DI && TARGET_VSX && reload_completed"
+ "TARGET_VSX && reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
@@ -8686,7 +8686,7 @@ (define_split
(define_split
[(set (match_operand:INT_ISA3 0 "altivec_register_operand" "")
(match_operand:INT_ISA3 1 "xxspltib_constant_split" ""))]
- "TARGET_UPPER_REGS_DI && TARGET_P9_VECTOR && reload_completed"
+ "TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
