This patch eliminates the TARGET_UPPER_REGS_{DF,SF} macros. The next patch
will eliminate TARGET_UPPER_REGS_DI.
I had to tune the optimization that turned load into FPR register and then move
to Altivec register (and the store equivalent) because it used
TARGET_UPPER_REGS_<MODE> to protect SFmode on power7. I split the upper
register patch for DImode because there were a few more cases (mostly involving
VSX small integer support), and I will submit the patch after this one.
As I'm posting this, the little endian power8 build has finished the bootstrap
and is beginning the test phase, and big endian power7 is on stage 2. Assuming
both systems show no regressions, is it ok to check this patch into the trunk?
As I mentioned, my next patch will eliminate TARGET_UPPER_REGS_DI. I will
probably tackle eliminating the VSX small integer option after that, and then
eliminating the ISA 3.0 d-form options.
2017-07-24 Michael Meissner <meiss...@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok):
Eliminate TARGET_UPPER_REGS_{DF,DI} usage.
* config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Poison macro.
(TARGET_UPPER_REGS_SF): Likewise.
* config/rs6000/rs6000.md (ALTIVEC_DFORM): Eliminate
TARGET_UPPER_REGS_{DF,SF,DI} usage in optimizing DF/SF/DI memory
references involving Altivec registers.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 250485)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -3216,22 +3216,12 @@ rs6000_init_hard_regno_mode_ok (bool glo
rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
if (TARGET_VSX_TIMODE)
rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
-
- if (TARGET_UPPER_REGS_DF) /*
DFmode */
- {
- rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS;
- rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS;
- }
- else
- rs6000_constraints[RS6000_CONSTRAINT_ws] = FLOAT_REGS;
-
- if (TARGET_UPPER_REGS_DI) /*
DImode */
- rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS;
- else
- rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS;
}
/* Add conditional constraints based on various options, to allow us to
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (revision 250485)
+++ gcc/config/rs6000/rs6000.h (working copy)
@@ -575,9 +575,11 @@ extern int rs6000_vector_align[];
and/or SFmode could go in the traditional Altivec registers. GCC 8.x
deleted
these options. In order to simplify the code, define the options in terms
of the base option (vsx, power8-vector). */
-#define TARGET_UPPER_REGS_DF TARGET_VSX
+#if (GCC_VERSION >= 3000)
+#pragma GCC poison TARGET_UPPER_REGS_DF TARGET_UPPER_REGS_SF
+#endif
+
#define TARGET_UPPER_REGS_DI TARGET_VSX
-#define TARGET_UPPER_REGS_SF TARGET_P8_VECTOR
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 250485)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -691,7 +691,7 @@ (define_code_attr SMINMAX [(smin "SM
;; D-form load to FPR register & move to Altivec register
;; Move Altivec register to FPR register and store
(define_mode_iterator ALTIVEC_DFORM [DF
- SF
+ (SF "TARGET_P8_VECTOR")
(DI "TARGET_POWERPC64")])
@@ -9766,7 +9766,7 @@ (define_peephole2
(match_operand:DF 1 "any_operand" ""))
(set (match_operand:DF 2 "gpc_reg_operand" "")
(match_dup 0))]
- "!TARGET_UPPER_REGS_DF
+ "!TARGET_VSX
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
@@ -9775,7 +9775,7 @@ (define_peephole2
(match_operand:SF 1 "any_operand" ""))
(set (match_operand:SF 2 "gpc_reg_operand" "")
(match_dup 0))]
- "!TARGET_UPPER_REGS_SF
+ "!TARGET_P8_VECTOR
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
@@ -13974,8 +13974,7 @@ (define_peephole2
(match_operand:ALTIVEC_DFORM 2 "simple_offsettable_mem_operand"))
(set (match_operand:ALTIVEC_DFORM 3 "altivec_register_operand")
(match_dup 1))]
- "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
- && peep2_reg_dead_p (2, operands[1])"
+ "TARGET_VSX && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
[(set (match_dup 0)
(match_dup 4))
(set (match_dup 3)
@@ -14011,8 +14010,7 @@ (define_peephole2
(match_operand:ALTIVEC_DFORM 2 "altivec_register_operand"))
(set (match_operand:ALTIVEC_DFORM 3 "simple_offsettable_mem_operand")
(match_dup 1))]
- "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
- && peep2_reg_dead_p (2, operands[1])"
+ "TARGET_VSX && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
[(set (match_dup 0)
(match_dup 4))
(set (match_dup 5)
