[PATCH, cleanup] Remove PowerPC -mupper-regs-* options

Michael Meissner Fri, 21 Jul 2017 23:47:19 -0700

The -mupper-regs-{df,di,sf} debug options that I added in previoius versions of
GCC to control whether DFmode, DImode, or SFmode could go in the traditional
Altivec registers has outlived its usefulness.  This patch deletes the
options.  I fixed up the various tests that used the option, and deleted
several tests that make no sense now that the options don't exist.


I have checked this with bootstrap builds and make check on a little endian
power8 system and a big endian power7 system.  There were no regressions in any
of the tests.

One thing that I did was continue to define __UPPER_REGS_{DF,SF,DI}__ that were
previously defined.  I can delete them if desired and perhaps poison the names
so that any use if flaged.

Future patches will include removal of the TARGET_UPPER_REGS_* macros in the
various files.  I also plan to remove -mvsx-small-integer, and the various
-mpower9-dform* options.

Is this ok for trunk?  At present, I do not intend to back port this to GCC 7
(but if the maintainers want that, I can do it).

[gcc]
2017-07-22  Michael Meissner  <meiss...@linux.vnet.ibm.com>

        * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Delete
        upper-regs options.
        (ISA_2_7_MASKS_SERVER): Likewise.
        (ISA_3_0_MASKS_IEEE): Likewise.
        (OTHER_P8_VECTOR_MASKS): Likewise.
        (OTHER_VSX_VECTOR_MASKS): Likewise.
        (POWERPC_MASKS): Likewise.
        (power7 cpu): Use ISA_2_6_MASKS_SERVER instead of using a
        duplicate list of options.
        * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Remove
        explicit -mupper-regs options.  Define __UPPER_REGS_*__ based on
        VSX or P8_VECTOR.
        * config/rs6000/rs6000.opt (-mvsx-scalar-memory): Delete
        -mupper-regs* options.  Delete -mvsx-scalar-memory, which was an
        alias for -mupper-regs-df.
        * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Likewise.
        (rs6000_init_hard_regno_mode_ok): Likewise.
        (rs6000_option_override_internal): Likewise.
        (rs6000_opt_masks): Likewise.
        * config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Define upper regs
        options in terms of whether -mvsx or -mpower8-vector was used.
        (TARGET_UPPER_REGS_DI): Likewise.
        (TARGET_UPPER_REGS_SF): Likewise.
        * doc/invoke.texi (RS/6000 and PowerPC Options): Delete the
        -mupper-regs-* options.

[gcc/testsuite]
2017-07-22  Michael Meissner  <meiss...@linux.vnet.ibm.com>

        * gcc.target/powerpc/pr65849-1.c: Delete, test no longer valid
        since the upper-regs options have been deleted.
        * gcc.target/powerpc/pr65849-2.c: Likewise.
        * gcc.target/powerpc/pr80099-1.c: Likewise.
        * gcc.target/powerpc/pr80099-2.c: Likewise.
        * gcc.target/powerpc/pr80099-3.c: Likewise.
        * gcc.target/powerpc/pr80099-4.c: Likewise.
        * gcc.target/powerpc/pr80099-5.c: Likewise.
        * gcc.target/powerpc/builtins-2-p9-runnable.c: Update test to
        support removal of the upper-regs options.
        * gcc.target/powerpc/p8vector-fp.c: Likewise.
        * gcc.target/powerpc/p8vector-ldst.c: Likewise.
        * gcc.target/powerpc/p9-dimode1.c: Likewise.
        * gcc.target/powerpc/p9-dimode2.c: Likewise.
        * gcc.target/powerpc/ppc-fpconv-1.c: Likewise.
        * gcc.target/powerpc/ppc-fpconv-10.c: Likewise.
        * gcc.target/powerpc/ppc-fpconv-5.c: Likewise.
        * gcc.target/powerpc/ppc-fpconv-9.c: Likewise.
        * gcc.target/powerpc/ppc-round.c: Likewise.
        * gcc.target/powerpc/pr71720.c: Likewise.
        * gcc.target/powerpc/pr72853.c: Likewise.
        * gcc.target/powerpc/pr79907.c: Likewise.
        * gcc.target/powerpc/pr78953.c: Likewise.
        * gcc.target/powerpc/upper-regs-df.c: Likewise.
        * gcc.target/powerpc/upper-regs-sf.c: Likewise.
        * gcc.target/powerpc/vec-extract-1.c: Likewise.
        * gcc.target/powerpc/vec-init-3.c: Likewise.
        * gcc.target/powerpc/vec-init-6.c: Likewise.
        * gcc.target/powerpc/vec-init-7.c: Likewise.
        * gcc.target/powerpc/vec-set-char.c: Likewise.
        * gcc.target/powerpc/vec-set-int.c: Likewise.
        * gcc.target/powerpc/vec-set-short.c: Likewise.



-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Index: gcc/config/rs6000/rs6000-cpus.def
===================================================================
--- gcc/config/rs6000/rs6000-cpus.def   
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)    
(revision 250405)
+++ gcc/config/rs6000/rs6000-cpus.def   (.../gcc/config/rs6000) (working copy)
@@ -44,9 +44,7 @@
 #define ISA_2_6_MASKS_SERVER   (ISA_2_5_MASKS_SERVER                   \
                                 | OPTION_MASK_POPCNTD                  \
                                 | OPTION_MASK_ALTIVEC                  \
-                                | OPTION_MASK_VSX                      \
-                                | OPTION_MASK_UPPER_REGS_DI            \
-                                | OPTION_MASK_UPPER_REGS_DF)
+                                | OPTION_MASK_VSX)
 
 /* For now, don't provide an embedded version of ISA 2.07.  */
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER                   \
@@ -58,7 +56,6 @@
                                 | OPTION_MASK_HTM                      \
                                 | OPTION_MASK_QUAD_MEMORY              \
                                 | OPTION_MASK_QUAD_MEMORY_ATOMIC       \
-                                | OPTION_MASK_UPPER_REGS_SF            \
                                 | OPTION_MASK_VSX_SMALL_INTEGER)
 
 /* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
@@ -79,9 +76,6 @@
                                 | OPTION_MASK_P8_VECTOR                \
                                 | OPTION_MASK_P9_VECTOR                \
                                 | OPTION_MASK_DIRECT_MOVE              \
-                                | OPTION_MASK_UPPER_REGS_DI            \
-                                | OPTION_MASK_UPPER_REGS_DF            \
-                                | OPTION_MASK_UPPER_REGS_SF            \
                                 | OPTION_MASK_VSX_SMALL_INTEGER)
 
 /* Flags that need to be turned off if -mno-power9-vector.  */
@@ -94,8 +88,7 @@
 #define OTHER_P8_VECTOR_MASKS  (OTHER_P9_VECTOR_MASKS                  \
                                 | OPTION_MASK_P9_VECTOR                \
                                 | OPTION_MASK_DIRECT_MOVE              \
-                                | OPTION_MASK_CRYPTO                   \
-                                | OPTION_MASK_UPPER_REGS_SF)           \
+                                | OPTION_MASK_CRYPTO)
 
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS                  \
@@ -103,8 +96,6 @@
                                 | OPTION_MASK_FLOAT128_KEYWORD         \
                                 | OPTION_MASK_FLOAT128_TYPE            \
                                 | OPTION_MASK_P8_VECTOR                \
-                                | OPTION_MASK_UPPER_REGS_DI            \
-                                | OPTION_MASK_UPPER_REGS_DF            \
                                 | OPTION_MASK_VSX_SMALL_INTEGER        \
                                 | OPTION_MASK_VSX_TIMODE)
 
@@ -160,9 +151,6 @@
                                 | OPTION_MASK_SOFT_FLOAT               \
                                 | OPTION_MASK_STRICT_ALIGN_OPTIONAL    \
                                 | OPTION_MASK_TOC_FUSION               \
-                                | OPTION_MASK_UPPER_REGS_DI            \
-                                | OPTION_MASK_UPPER_REGS_DF            \
-                                | OPTION_MASK_UPPER_REGS_SF            \
                                 | OPTION_MASK_VSX                      \
                                 | OPTION_MASK_VSX_SMALL_INTEGER        \
                                 | OPTION_MASK_VSX_TIMODE)
@@ -251,11 +239,7 @@ RS6000_CPU ("power6", PROCESSOR_POWER6, 
 RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
            | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
            | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
-RS6000_CPU ("power7", PROCESSOR_POWER7,   /* Don't add MASK_ISEL by default */
-           POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
-           | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
-           | MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF
-           | OPTION_MASK_UPPER_REGS_DI)
+RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
 RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
 RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
 RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt        
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)    
(revision 250405)
+++ gcc/config/rs6000/rs6000.opt        (.../gcc/config/rs6000) (working copy)
@@ -200,9 +200,6 @@ mvsx-scalar-double
 Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1)
 ; If -mvsx, use VSX arithmetic instructions for DFmode (on by default)
 
-mvsx-scalar-memory
-Target Undocumented Report Alias(mupper-regs-df)
-
 mvsx-align-128
 Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
 ; If -mvsx, set alignment to 128 bits instead of 32/64
@@ -549,22 +546,6 @@ mcompat-align-parm
 Target Report Var(rs6000_compat_align_parm) Init(0) Save
 Generate aggregate parameter passing code with at most 64-bit alignment.
 
-mupper-regs-df
-Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
-Allow double variables in upper registers with -mcpu=power7 or -mvsx.
-
-mupper-regs-sf
-Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
-Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector.
-
-mupper-regs
-Target Report Var(TARGET_UPPER_REGS) Init(-1) Save
-Allow float/double variables in upper registers if cpu allows it.
-
-mupper-regs-di
-Target Report Mask(UPPER_REGS_DI) Var(rs6000_isa_flags)
-Allow 64-bit integer variables in upper registers with -mcpu=power7 or -mvsx.
-
 moptimize-swaps
 Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
 Analyze and remove doubleword swaps from VSX computations.
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- gcc/config/rs6000/rs6000-c.c        
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)    
(revision 250405)
+++ gcc/config/rs6000/rs6000-c.c        (.../gcc/config/rs6000) (working copy)
@@ -575,39 +575,20 @@ rs6000_target_modify_macros (bool define
      2. If TARGET_ALTIVEC is turned off.  */
   if ((flags & OPTION_MASK_CRYPTO) != 0)
     rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
-  /* Note that the OPTION_MASK_UPPER_REGS_DF flag is automatically
-     turned on in the following conditions:
-     1. If TARGET_UPPER_REGS is explicitly turned on and
-       TARGET_VSX is turned on and OPTION_MASK_UPPER_REGS_DF is not
-       explicitly turned off.  Hereafter, the
-       OPTION_MASK_UPPER_REGS_DF flag is considered to have been
-       explicitly set.
-     Note that the OPTION_MASK_UPPER_REGS_DF flag is automatically
-     turned off in the following conditions:
-     1. If TARGET_UPPER_REGS is explicitly turned off and TARGET_VSX
-       is turned on and OPTION_MASK_UPPER_REGS_DF is not explicitly
-       turned on.  Hereafter, the OPTION_MASK_UPPER_REGS_DF flag is
-       considered to have been explicitly cleared.
-     2. If TARGET_UPPER_REGS_DF is turned on but TARGET_VSX is turned
-       off.  */
-  if ((flags & OPTION_MASK_UPPER_REGS_DF) != 0)
-    rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DF__");
-  /* Note that the OPTION_MASK_UPPER_REGS_SF flag is automatically
-     turned on in the following conditions:
-     1. If TARGET_UPPER_REGS is explicitly turned on and
-       TARGET_P8_VECTOR is on and OPTION_MASK_UPPER_REGS_SF is not
-       turned off explicitly.  Hereafter, the
-       OPTION_MASK_UPPER_REGS_SF flag is considered to have been
-       explicitly set.
-     Note that the OPTION_MASK_UPPER_REGS_SF flag is automatically
-     turned off in the following conditions:
-     1. If TARGET_UPPER_REGS is explicitly turned off and
-       TARGET_P8_VECTOR is on and OPTION_MASK_UPPER_REGS_SF is not
-       turned off explicitly.  Hereafter, the
-       OPTION_MASK_UPPER_REGS_SF flag is considered to have been
-       explicitly cleared.
-     2. If TARGET_P8_VECTOR is off.  */
-  if ((flags & OPTION_MASK_UPPER_REGS_SF) != 0)
+  /* Note, previously __UPPER_REGS_DF__ was defined if the option
+     -mupper-regs-df was used and it was on by default for -mvsx.  That option
+     is now eliminated, so set __UPPER_REGS_DF__ based on whether VSX was
+     set.  */
+  if ((flags & OPTION_MASK_VSX) != 0)
+    {
+      rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DF__");
+      rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DI__");
+    }
+  /* Note, previously __UPPER_REGS_SF__ was defined if the option
+     -mupper-regs-df was used and it was on by default for -mvsx.  That option
+     is now eliminated, so set __UPPER_REGS_DF__ based on whether VSX was
+     set.  */
+  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
     rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__");
 
   /* options from the builtin masks.  */
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c  
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)    
(revision 250405)
+++ gcc/config/rs6000/rs6000.c  (.../gcc/config/rs6000) (working copy)
@@ -2908,8 +2908,7 @@ rs6000_setup_reg_addr_masks (void)
                  && !FLOAT128_VECTOR_P (m2)
                  && !complex_p
                  && !small_int_vsx_p
-                 && (m2 != DFmode || !TARGET_UPPER_REGS_DF)
-                 && (m2 != SFmode || !TARGET_UPPER_REGS_SF))
+                 && (m2 != DFmode || !TARGET_UPPER_REGS_DF))
                {
                  addr_mask |= RELOAD_REG_PRE_INCDEC;
 
@@ -3263,7 +3262,7 @@ rs6000_init_hard_regno_mode_ok (bool glo
       rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
     }
 
-  if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF)                        /* 
SFmode  */
+  if (TARGET_P8_VECTOR)                                                /* 
SFmode  */
     {
       rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
       rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
@@ -3458,13 +3457,13 @@ rs6000_init_hard_regno_mode_ok (bool glo
            }
        }
 
-      if (TARGET_UPPER_REGS_DF)
-       reg_addr[DFmode].scalar_in_vmx_p = true;
-
-      if (TARGET_UPPER_REGS_DI)
-       reg_addr[DImode].scalar_in_vmx_p = true;
+      if (TARGET_VSX)
+       {
+         reg_addr[DFmode].scalar_in_vmx_p = true;
+         reg_addr[DImode].scalar_in_vmx_p = true;
+       }
 
-      if (TARGET_UPPER_REGS_SF)
+      if (TARGET_P8_VECTOR)
        reg_addr[SFmode].scalar_in_vmx_p = true;
 
       if (TARGET_VSX_SMALL_INTEGER)
@@ -4277,18 +4276,10 @@ rs6000_option_override_internal (bool gl
        {
          if (cpu_index == PROCESSOR_POWER9)
            {
-             /* legacy behavior: allow -mcpu-power9 with certain
+             /* legacy behavior: allow -mcpu=power9 with certain
                 capabilities explicitly disabled.  */
              rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-             /* However, reject this automatic fix if certain
-                capabilities required for TARGET_P9_MINMAX support
-                have been explicitly disabled.  */
-             if (((OPTION_MASK_VSX | OPTION_MASK_UPPER_REGS_SF
-                   | OPTION_MASK_UPPER_REGS_DF) & rs6000_isa_flags)
-                 != (OPTION_MASK_VSX | OPTION_MASK_UPPER_REGS_SF
-                     | OPTION_MASK_UPPER_REGS_DF))
-               error ("-mpower9-minmax incompatible with explicitly disabled 
options");
-               }
+           }
          else
            error ("Power9 target option is incompatible with -mcpu=<xxx> for "
                   "<xxx> less than power9");
@@ -4374,73 +4365,6 @@ rs6000_option_override_internal (bool gl
       rs6000_isa_flags &= ~OPTION_MASK_DFP;
     }
 
-  /* Allow an explicit -mupper-regs to set -mupper-regs-df, -mupper-regs-di,
-     and -mupper-regs-sf, depending on the cpu, unless the user explicitly also
-     set the individual option.  */
-  if (TARGET_UPPER_REGS > 0)
-    {
-      if (TARGET_VSX
-         && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF))
-       {
-         rs6000_isa_flags |= OPTION_MASK_UPPER_REGS_DF;
-         rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DF;
-       }
-      if (TARGET_VSX
-         && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DI))
-       {
-         rs6000_isa_flags |= OPTION_MASK_UPPER_REGS_DI;
-         rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DI;
-       }
-      if (TARGET_P8_VECTOR
-         && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF))
-       {
-         rs6000_isa_flags |= OPTION_MASK_UPPER_REGS_SF;
-         rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_SF;
-       }
-    }
-  else if (TARGET_UPPER_REGS == 0)
-    {
-      if (TARGET_VSX
-         && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF))
-       {
-         rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DF;
-         rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DF;
-       }
-      if (TARGET_VSX
-         && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DI))
-       {
-         rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DI;
-         rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DI;
-       }
-      if (TARGET_P8_VECTOR
-         && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF))
-       {
-         rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_SF;
-         rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_SF;
-       }
-    }
-
-  if (TARGET_UPPER_REGS_DF && !TARGET_VSX)
-    {
-      if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
-       error ("-mupper-regs-df requires -mvsx");
-      rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DF;
-    }
-
-  if (TARGET_UPPER_REGS_DI && !TARGET_VSX)
-    {
-      if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DI)
-       error ("-mupper-regs-di requires -mvsx");
-      rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DI;
-    }
-
-  if (TARGET_UPPER_REGS_SF && !TARGET_P8_VECTOR)
-    {
-      if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF)
-       error ("-mupper-regs-sf requires -mpower8-vector");
-      rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_SF;
-    }
-
   /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
      silently turn off quad memory mode.  */
   if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
@@ -4649,24 +4573,6 @@ rs6000_option_override_internal (bool gl
        }
     }
 
-  if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_DF)
-    {
-      /* We prefer to not mention undocumented options in
-        error messages.  However, if users have managed to select
-        power9-dform without selecting upper-regs-df, they
-        already know about undocumented flags.  */
-      if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
-       error ("-mpower9-dform requires -mupper-regs-df");
-      rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
-    }
-
-  if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_SF)
-    {
-      if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF)
-       error ("-mpower9-dform requires -mupper-regs-sf");
-      rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
-    }
-
   /* Enable LRA by default.  */
   if ((rs6000_isa_flags_explicit & OPTION_MASK_LRA) == 0)
     rs6000_isa_flags |= OPTION_MASK_LRA;
@@ -36358,9 +36264,6 @@ static struct rs6000_opt_mask const rs60
   { "string",                  OPTION_MASK_STRING,             false, true  },
   { "toc-fusion",              OPTION_MASK_TOC_FUSION,         false, true  },
   { "update",                  OPTION_MASK_NO_UPDATE,          true , true  },
-  { "upper-regs-di",           OPTION_MASK_UPPER_REGS_DI,      false, true  },
-  { "upper-regs-df",           OPTION_MASK_UPPER_REGS_DF,      false, true  },
-  { "upper-regs-sf",           OPTION_MASK_UPPER_REGS_SF,      false, true  },
   { "vsx",                     OPTION_MASK_VSX,                false, true  },
   { "vsx-small-integer",       OPTION_MASK_VSX_SMALL_INTEGER,  false, true  },
   { "vsx-timode",              OPTION_MASK_VSX_TIMODE,         false, true  },
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h  
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)    
(revision 250405)
+++ gcc/config/rs6000/rs6000.h  (.../gcc/config/rs6000) (working copy)
@@ -571,6 +571,14 @@ extern int rs6000_vector_align[];
 
 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
 
+/* We previously had -mupper-regs-{df,di,sf} to control whether DFmode, DImode,
+   and/or SFmode could go in the traditional Altivec registers.  GCC 8.x 
deleted
+   these options.  In order to simplify the code, define the options in terms
+   of the base option (vsx, power8-vector).  */
+#define TARGET_UPPER_REGS_DF   TARGET_VSX
+#define TARGET_UPPER_REGS_DI   TARGET_VSX
+#define TARGET_UPPER_REGS_SF   TARGET_P8_VECTOR
+
 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
    Enable 32-bit fcfid's on any of the switches for newer ISA machines or
    XILINX.  */
@@ -602,7 +610,6 @@ extern int rs6000_vector_align[];
 #define TARGET_VEXTRACTUB      (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
                                 && TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
 
-
 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI).  */
 #define TARGET_NO_SF_SUBREG    TARGET_DIRECT_MOVE_64BIT
 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi 
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/doc)      (revision 
250405)
+++ gcc/doc/invoke.texi (.../gcc/doc)   (working copy)
@@ -1045,9 +1045,6 @@ See RS/6000 and PowerPC Options.
 -mquad-memory  -mno-quad-memory @gol
 -mquad-memory-atomic  -mno-quad-memory-atomic @gol
 -mcompat-align-parm  -mno-compat-align-parm @gol
--mupper-regs-df  -mno-upper-regs-df  -mupper-regs-sf  -mno-upper-regs-sf @gol
--mupper-regs-di  -mno-upper-regs-di @gol
--mupper-regs  -mno-upper-regs @gol
 -mfloat128  -mno-float128  -mfloat128-hardware  -mno-float128-hardware @gol
 -mgnu-attribute  -mno-gnu-attribute @gol
 -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol
@@ -21899,50 +21896,6 @@ Generate code that uses (does not use) t
 instructions.  The @option{-mquad-memory-atomic} option requires use of
 64-bit mode.
 
-@item -mupper-regs-di
-@itemx -mno-upper-regs-di
-@opindex mupper-regs-di
-@opindex mno-upper-regs-di
-Generate code that uses (does not use) the scalar instructions that
-target all 64 registers in the vector/scalar floating point register
-set that were added in version 2.06 of the PowerPC ISA when processing
-integers.  @option{-mupper-regs-di} is turned on by default if you use
-any of the @option{-mcpu=power7}, @option{-mcpu=power8},
-@option{-mcpu=power9}, or @option{-mvsx} options.
-
-@item -mupper-regs-df
-@itemx -mno-upper-regs-df
-@opindex mupper-regs-df
-@opindex mno-upper-regs-df
-Generate code that uses (does not use) the scalar double precision
-instructions that target all 64 registers in the vector/scalar
-floating point register set that were added in version 2.06 of the
-PowerPC ISA.  @option{-mupper-regs-df} is turned on by default if you
-use any of the @option{-mcpu=power7}, @option{-mcpu=power8},
-@option{-mcpu=power9}, or @option{-mvsx} options.
-
-@item -mupper-regs-sf
-@itemx -mno-upper-regs-sf
-@opindex mupper-regs-sf
-@opindex mno-upper-regs-sf
-Generate code that uses (does not use) the scalar single precision
-instructions that target all 64 registers in the vector/scalar
-floating point register set that were added in version 2.07 of the
-PowerPC ISA.  @option{-mupper-regs-sf} is turned on by default if you
-use either of the @option{-mcpu=power8}, @option{-mpower8-vector}, or
-@option{-mcpu=power9} options.
-
-@item -mupper-regs
-@itemx -mno-upper-regs
-@opindex mupper-regs
-@opindex mno-upper-regs
-Generate code that uses (does not use) the scalar
-instructions that target all 64 registers in the vector/scalar
-floating point register set, depending on the model of the machine.
-
-If the @option{-mno-upper-regs} option is used, it turns off both
-@option{-mupper-regs-sf} and @option{-mupper-regs-df} options.
-
 @item -mfloat128
 @itemx -mno-float128
 @opindex mfloat128
Index: gcc/testsuite/gcc.target/powerpc/pr80099-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-1.c        
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-1.c        
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,12 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */
-
-/* PR target/80099: compiler internal error if -mno-upper-regs-sf used.  */
-
-int a;
-int int_from_mem (vector float *c)
-{
-  return __builtin_vec_extract (*c, a);
-}
Index: gcc/testsuite/gcc.target/powerpc/pr80099-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-2.c        
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-2.c        
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf.  Test for all variable
-   extract types with various -mno-upper-regs-* options.  */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
-  return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
-  return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
-  return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
-  return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
-  return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
-  return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
-  return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
-  return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
-  return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
-  return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
-  return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
-  return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
-  return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
-  return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
-  return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
-  return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
-  return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
-  return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
-  return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
-  return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/p8vector-fp.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p8vector-fp.c      
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/p8vector-fp.c      
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf 
-fno-math-errno" } */
+/* { dg-options "-mcpu=power8 -O2 -fno-math-errno" } */
 
 float abs_sf (float *p)
 {
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c     
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c     
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -2,12 +2,12 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power7" } } */
-/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "fctidz" 2 } } */
-/* { dg-final { scan-assembler-not "lwz" } } */
-/* { dg-final { scan-assembler-not "stw" } } */
-/* { dg-final { scan-assembler-not "ld " } } */
-/* { dg-final { scan-assembler-not "std" } } */
+/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */
+/* { dg-final { scan-assembler-not   {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not   {\mstw\M} } } */
+/* { dg-final { scan-assembler-not   {\mld\M}  } } */
+/* { dg-final { scan-assembler-not   {\mstd\M} } } */
 
 void float_to_llong  (long long *dest, float  src) { *dest = (long long) src; }
 void double_to_llong (long long *dest, double src) { *dest = (long long) src; }
Index: gcc/testsuite/gcc.target/powerpc/pr80099-3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-3.c        
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-3.c        
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-df" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf.  Test for all variable
-   extract types with various -mno-upper-regs-* options.  */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
-  return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
-  return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
-  return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
-  return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
-  return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
-  return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
-  return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
-  return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
-  return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
-  return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
-  return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
-  return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
-  return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
-  return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
-  return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
-  return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
-  return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
-  return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
-  return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
-  return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c    
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c    
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -2,10 +2,10 @@
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */
+/* { dg-options "-mcpu=power8 -O2" } */
 
-/* Test for the -mupper-regs-df option to make sure double values are allocated
-   to the Altivec registers as well as the traditional FPR registers.  */
+/* Test make sure single precision values are allocated to the Altivec
+   registers as well as the traditional FPR registers.  */
 
 #ifndef TYPE
 #define TYPE float
Index: gcc/testsuite/gcc.target/powerpc/p9-dimode1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p9-dimode1.c       
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/p9-dimode1.c       
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
 
 /* Verify P9 changes to allow DImode into Altivec registers, and generate
    constants using XXSPLTIB.  */
@@ -43,8 +43,8 @@ p9_minus_1 (void)
   return ret;
 }
 
-/* { dg-final { scan-assembler     "\[ \t\]xxspltib" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]mtvsrd"   } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lfd"  } } */
-/* { dg-final { scan-assembler-not "\[ \t\]ld"   } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lxsd" } } */
+/* { dg-final { scan-assembler     {\mxxspltib\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrd\M}   } } */
+/* { dg-final { scan-assembler-not {\mlfd\M}      } } */
+/* { dg-final { scan-assembler-not {\mld\M}       } } */
+/* { dg-final { scan-assembler-not {\mlxsd\M}     } } */
Index: gcc/testsuite/gcc.target/powerpc/pr80099-4.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-4.c        
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-4.c        
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-di" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf.  Test for all variable
-   extract types with various -mno-upper-regs-* options.  */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
-  return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
-  return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
-  return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
-  return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
-  return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
-  return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
-  return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
-  return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
-  return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
-  return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
-  return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
-  return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
-  return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
-  return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
-  return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
-  return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
-  return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
-  return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
-  return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
-  return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/p9-dimode2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p9-dimode2.c       
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/p9-dimode2.c       
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
 
 /* Verify that large integer constants are loaded via direct move instead of 
being
    loaded from memory.  */
@@ -21,7 +21,7 @@ p9_large (void)
   return ret;
 }
 
-/* { dg-final { scan-assembler     "\[ \t\]mtvsrd" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]ld"     } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lfd"    } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lxsd"   } } */
+/* { dg-final { scan-assembler     {\mmtvsrd\M} } } */
+/* { dg-final { scan-assembler-not {\mld\M}     } } */
+/* { dg-final { scan-assembler-not {\mlfd\M}    } } */
+/* { dg-final { scan-assembler-not {\mlxsd\M}   } } */
Index: gcc/testsuite/gcc.target/powerpc/pr72853.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr72853.c  
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr72853.c  
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O3 -mupper-regs-df -mupper-regs-sf 
-funroll-loops" } */
+/* { dg-options "-mcpu=power9 -O3 -funroll-loops" } */
 
 /* derived from 20021120-1.c, compiled for -mcpu=power9.  */
 
Index: gcc/testsuite/gcc.target/powerpc/pr80099-5.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-5.c        
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-5.c        
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf.  Test for all variable
-   extract types with various -mno-upper-regs-* options.  */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
-  return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
-  return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
-  return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
-  return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
-  return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
-  return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
-  return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
-  return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
-  return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
-  return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
-  return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
-  return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
-  return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
-  return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
-  return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
-  return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
-  return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
-  return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
-  return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
-  return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/pr79907.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr79907.c  
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr79907.c  
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O3 -mno-upper-regs-df" } */
+/* { dg-options "-mcpu=power8 -O3" } */
 
 int foo (short a[], int x)
 {
Index: gcc/testsuite/gcc.target/powerpc/pr65849-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr65849-1.c        
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr65849-1.c        
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,728 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power7" } } */
-/* { dg-options "-mcpu=power7 -O2 -mno-upper-regs-df" } */
-
-/* Test whether we can enable the -mupper-regs-df with target pragmas.  Make
-   sure double values are allocated to the Altivec registers as well as the
-   traditional FPR registers.  */
-
-#ifndef TYPE
-#define TYPE double
-#endif
-
-#ifndef MASK_TYPE
-#define MASK_TYPE unsigned long long
-#endif
-
-#define MASK_ONE       ((MASK_TYPE)1)
-#define ZERO           ((TYPE) 0.0)
-
-#pragma GCC target ("upper-regs-df")
-TYPE
-test_add (const MASK_TYPE *add_mask, const TYPE *add_values,
-         const MASK_TYPE *sub_mask, const TYPE *sub_values,
-         const MASK_TYPE *mul_mask, const TYPE *mul_values,
-         const MASK_TYPE *div_mask, const TYPE *div_values,
-         const MASK_TYPE *eq0_mask, int *eq0_ptr)
-{
-  TYPE value;
-  TYPE value00 = ZERO;
-  TYPE value01 = ZERO;
-  TYPE value02 = ZERO;
-  TYPE value03 = ZERO;
-  TYPE value04 = ZERO;
-  TYPE value05 = ZERO;
-  TYPE value06 = ZERO;
-  TYPE value07 = ZERO;
-  TYPE value08 = ZERO;
-  TYPE value09 = ZERO;
-  TYPE value10 = ZERO;
-  TYPE value11 = ZERO;
-  TYPE value12 = ZERO;
-  TYPE value13 = ZERO;
-  TYPE value14 = ZERO;
-  TYPE value15 = ZERO;
-  TYPE value16 = ZERO;
-  TYPE value17 = ZERO;
-  TYPE value18 = ZERO;
-  TYPE value19 = ZERO;
-  TYPE value20 = ZERO;
-  TYPE value21 = ZERO;
-  TYPE value22 = ZERO;
-  TYPE value23 = ZERO;
-  TYPE value24 = ZERO;
-  TYPE value25 = ZERO;
-  TYPE value26 = ZERO;
-  TYPE value27 = ZERO;
-  TYPE value28 = ZERO;
-  TYPE value29 = ZERO;
-  TYPE value30 = ZERO;
-  TYPE value31 = ZERO;
-  TYPE value32 = ZERO;
-  TYPE value33 = ZERO;
-  TYPE value34 = ZERO;
-  TYPE value35 = ZERO;
-  TYPE value36 = ZERO;
-  TYPE value37 = ZERO;
-  TYPE value38 = ZERO;
-  TYPE value39 = ZERO;
-  MASK_TYPE mask;
-  int eq0;
-
-  while ((mask = *add_mask++) != 0)
-    {
-      value = *add_values++;
-
-      __asm__ (" #reg %0" : "+d" (value));
-
-      if ((mask & (MASK_ONE <<  0)) != 0)
-       value00 += value;
-
-      if ((mask & (MASK_ONE <<  1)) != 0)
-       value01 += value;
-
-      if ((mask & (MASK_ONE <<  2)) != 0)
-       value02 += value;
-
-      if ((mask & (MASK_ONE <<  3)) != 0)
-       value03 += value;
-
-      if ((mask & (MASK_ONE <<  4)) != 0)
-       value04 += value;
-
-      if ((mask & (MASK_ONE <<  5)) != 0)
-       value05 += value;
-
-      if ((mask & (MASK_ONE <<  6)) != 0)
-       value06 += value;
-
-      if ((mask & (MASK_ONE <<  7)) != 0)
-       value07 += value;
-
-      if ((mask & (MASK_ONE <<  8)) != 0)
-       value08 += value;
-
-      if ((mask & (MASK_ONE <<  9)) != 0)
-       value09 += value;
-
-      if ((mask & (MASK_ONE << 10)) != 0)
-       value10 += value;
-
-      if ((mask & (MASK_ONE << 11)) != 0)
-       value11 += value;
-
-      if ((mask & (MASK_ONE << 12)) != 0)
-       value12 += value;
-
-      if ((mask & (MASK_ONE << 13)) != 0)
-       value13 += value;
-
-      if ((mask & (MASK_ONE << 14)) != 0)
-       value14 += value;
-
-      if ((mask & (MASK_ONE << 15)) != 0)
-       value15 += value;
-
-      if ((mask & (MASK_ONE << 16)) != 0)
-       value16 += value;
-
-      if ((mask & (MASK_ONE << 17)) != 0)
-       value17 += value;
-
-      if ((mask & (MASK_ONE << 18)) != 0)
-       value18 += value;
-
-      if ((mask & (MASK_ONE << 19)) != 0)
-       value19 += value;
-
-      if ((mask & (MASK_ONE << 20)) != 0)
-       value20 += value;
-
-      if ((mask & (MASK_ONE << 21)) != 0)
-       value21 += value;
-
-      if ((mask & (MASK_ONE << 22)) != 0)
-       value22 += value;
-
-      if ((mask & (MASK_ONE << 23)) != 0)
-       value23 += value;
-
-      if ((mask & (MASK_ONE << 24)) != 0)
-       value24 += value;
-
-      if ((mask & (MASK_ONE << 25)) != 0)
-       value25 += value;
-
-      if ((mask & (MASK_ONE << 26)) != 0)
-       value26 += value;
-
-      if ((mask & (MASK_ONE << 27)) != 0)
-       value27 += value;
-
-      if ((mask & (MASK_ONE << 28)) != 0)
-       value28 += value;
-
-      if ((mask & (MASK_ONE << 29)) != 0)
-       value29 += value;
-
-      if ((mask & (MASK_ONE << 30)) != 0)
-       value30 += value;
-
-      if ((mask & (MASK_ONE << 31)) != 0)
-       value31 += value;
-
-      if ((mask & (MASK_ONE << 32)) != 0)
-       value32 += value;
-
-      if ((mask & (MASK_ONE << 33)) != 0)
-       value33 += value;
-
-      if ((mask & (MASK_ONE << 34)) != 0)
-       value34 += value;
-
-      if ((mask & (MASK_ONE << 35)) != 0)
-       value35 += value;
-
-      if ((mask & (MASK_ONE << 36)) != 0)
-       value36 += value;
-
-      if ((mask & (MASK_ONE << 37)) != 0)
-       value37 += value;
-
-      if ((mask & (MASK_ONE << 38)) != 0)
-       value38 += value;
-
-      if ((mask & (MASK_ONE << 39)) != 0)
-       value39 += value;
-    }
-
-  while ((mask = *sub_mask++) != 0)
-    {
-      value = *sub_values++;
-
-      __asm__ (" #reg %0" : "+d" (value));
-
-      if ((mask & (MASK_ONE <<  0)) != 0)
-       value00 -= value;
-
-      if ((mask & (MASK_ONE <<  1)) != 0)
-       value01 -= value;
-
-      if ((mask & (MASK_ONE <<  2)) != 0)
-       value02 -= value;
-
-      if ((mask & (MASK_ONE <<  3)) != 0)
-       value03 -= value;
-
-      if ((mask & (MASK_ONE <<  4)) != 0)
-       value04 -= value;
-
-      if ((mask & (MASK_ONE <<  5)) != 0)
-       value05 -= value;
-
-      if ((mask & (MASK_ONE <<  6)) != 0)
-       value06 -= value;
-
-      if ((mask & (MASK_ONE <<  7)) != 0)
-       value07 -= value;
-
-      if ((mask & (MASK_ONE <<  8)) != 0)
-       value08 -= value;
-
-      if ((mask & (MASK_ONE <<  9)) != 0)
-       value09 -= value;
-
-      if ((mask & (MASK_ONE << 10)) != 0)
-       value10 -= value;
-
-      if ((mask & (MASK_ONE << 11)) != 0)
-       value11 -= value;
-
-      if ((mask & (MASK_ONE << 12)) != 0)
-       value12 -= value;
-
-      if ((mask & (MASK_ONE << 13)) != 0)
-       value13 -= value;
-
-      if ((mask & (MASK_ONE << 14)) != 0)
-       value14 -= value;
-
-      if ((mask & (MASK_ONE << 15)) != 0)
-       value15 -= value;
-
-      if ((mask & (MASK_ONE << 16)) != 0)
-       value16 -= value;
-
-      if ((mask & (MASK_ONE << 17)) != 0)
-       value17 -= value;
-
-      if ((mask & (MASK_ONE << 18)) != 0)
-       value18 -= value;
-
-      if ((mask & (MASK_ONE << 19)) != 0)
-       value19 -= value;
-
-      if ((mask & (MASK_ONE << 20)) != 0)
-       value20 -= value;
-
-      if ((mask & (MASK_ONE << 21)) != 0)
-       value21 -= value;
-
-      if ((mask & (MASK_ONE << 22)) != 0)
-       value22 -= value;
-
-      if ((mask & (MASK_ONE << 23)) != 0)
-       value23 -= value;
-
-      if ((mask & (MASK_ONE << 24)) != 0)
-       value24 -= value;
-
-      if ((mask & (MASK_ONE << 25)) != 0)
-       value25 -= value;
-
-      if ((mask & (MASK_ONE << 26)) != 0)
-       value26 -= value;
-
-      if ((mask & (MASK_ONE << 27)) != 0)
-       value27 -= value;
-
-      if ((mask & (MASK_ONE << 28)) != 0)
-       value28 -= value;
-
-      if ((mask & (MASK_ONE << 29)) != 0)
-       value29 -= value;
-
-      if ((mask & (MASK_ONE << 30)) != 0)
-       value30 -= value;
-
-      if ((mask & (MASK_ONE << 31)) != 0)
-       value31 -= value;
-
-      if ((mask & (MASK_ONE << 32)) != 0)
-       value32 -= value;
-
-      if ((mask & (MASK_ONE << 33)) != 0)
-       value33 -= value;
-
-      if ((mask & (MASK_ONE << 34)) != 0)
-       value34 -= value;
-
-      if ((mask & (MASK_ONE << 35)) != 0)
-       value35 -= value;
-
-      if ((mask & (MASK_ONE << 36)) != 0)
-       value36 -= value;
-
-      if ((mask & (MASK_ONE << 37)) != 0)
-       value37 -= value;
-
-      if ((mask & (MASK_ONE << 38)) != 0)
-       value38 -= value;
-
-      if ((mask & (MASK_ONE << 39)) != 0)
-       value39 -= value;
-    }
-
-  while ((mask = *mul_mask++) != 0)
-    {
-      value = *mul_values++;
-
-      __asm__ (" #reg %0" : "+d" (value));
-
-      if ((mask & (MASK_ONE <<  0)) != 0)
-       value00 *= value;
-
-      if ((mask & (MASK_ONE <<  1)) != 0)
-       value01 *= value;
-
-      if ((mask & (MASK_ONE <<  2)) != 0)
-       value02 *= value;
-
-      if ((mask & (MASK_ONE <<  3)) != 0)
-       value03 *= value;
-
-      if ((mask & (MASK_ONE <<  4)) != 0)
-       value04 *= value;
-
-      if ((mask & (MASK_ONE <<  5)) != 0)
-       value05 *= value;
-
-      if ((mask & (MASK_ONE <<  6)) != 0)
-       value06 *= value;
-
-      if ((mask & (MASK_ONE <<  7)) != 0)
-       value07 *= value;
-
-      if ((mask & (MASK_ONE <<  8)) != 0)
-       value08 *= value;
-
-      if ((mask & (MASK_ONE <<  9)) != 0)
-       value09 *= value;
-
-      if ((mask & (MASK_ONE << 10)) != 0)
-       value10 *= value;
-
-      if ((mask & (MASK_ONE << 11)) != 0)
-       value11 *= value;
-
-      if ((mask & (MASK_ONE << 12)) != 0)
-       value12 *= value;
-
-      if ((mask & (MASK_ONE << 13)) != 0)
-       value13 *= value;
-
-      if ((mask & (MASK_ONE << 14)) != 0)
-       value14 *= value;
-
-      if ((mask & (MASK_ONE << 15)) != 0)
-       value15 *= value;
-
-      if ((mask & (MASK_ONE << 16)) != 0)
-       value16 *= value;
-
-      if ((mask & (MASK_ONE << 17)) != 0)
-       value17 *= value;
-
-      if ((mask & (MASK_ONE << 18)) != 0)
-       value18 *= value;
-
-      if ((mask & (MASK_ONE << 19)) != 0)
-       value19 *= value;
-
-      if ((mask & (MASK_ONE << 20)) != 0)
-       value20 *= value;
-
-      if ((mask & (MASK_ONE << 21)) != 0)
-       value21 *= value;
-
-      if ((mask & (MASK_ONE << 22)) != 0)
-       value22 *= value;
-
-      if ((mask & (MASK_ONE << 23)) != 0)
-       value23 *= value;
-
-      if ((mask & (MASK_ONE << 24)) != 0)
-       value24 *= value;
-
-      if ((mask & (MASK_ONE << 25)) != 0)
-       value25 *= value;
-
-      if ((mask & (MASK_ONE << 26)) != 0)
-       value26 *= value;
-
-      if ((mask & (MASK_ONE << 27)) != 0)
-       value27 *= value;
-
-      if ((mask & (MASK_ONE << 28)) != 0)
-       value28 *= value;
-
-      if ((mask & (MASK_ONE << 29)) != 0)
-       value29 *= value;
-
-      if ((mask & (MASK_ONE << 30)) != 0)
-       value30 *= value;
-
-      if ((mask & (MASK_ONE << 31)) != 0)
-       value31 *= value;
-
-      if ((mask & (MASK_ONE << 32)) != 0)
-       value32 *= value;
-
-      if ((mask & (MASK_ONE << 33)) != 0)
-       value33 *= value;
-
-      if ((mask & (MASK_ONE << 34)) != 0)
-       value34 *= value;
-
-      if ((mask & (MASK_ONE << 35)) != 0)
-       value35 *= value;
-
-      if ((mask & (MASK_ONE << 36)) != 0)
-       value36 *= value;
-
-      if ((mask & (MASK_ONE << 37)) != 0)
-       value37 *= value;
-
-      if ((mask & (MASK_ONE << 38)) != 0)
-       value38 *= value;
-
-      if ((mask & (MASK_ONE << 39)) != 0)
-       value39 *= value;
-    }
-
-  while ((mask = *div_mask++) != 0)
-    {
-      value = *div_values++;
-
-      __asm__ (" #reg %0" : "+d" (value));
-
-      if ((mask & (MASK_ONE <<  0)) != 0)
-       value00 /= value;
-
-      if ((mask & (MASK_ONE <<  1)) != 0)
-       value01 /= value;
-
-      if ((mask & (MASK_ONE <<  2)) != 0)
-       value02 /= value;
-
-      if ((mask & (MASK_ONE <<  3)) != 0)
-       value03 /= value;
-
-      if ((mask & (MASK_ONE <<  4)) != 0)
-       value04 /= value;
-
-      if ((mask & (MASK_ONE <<  5)) != 0)
-       value05 /= value;
-
-      if ((mask & (MASK_ONE <<  6)) != 0)
-       value06 /= value;
-
-      if ((mask & (MASK_ONE <<  7)) != 0)
-       value07 /= value;
-
-      if ((mask & (MASK_ONE <<  8)) != 0)
-       value08 /= value;
-
-      if ((mask & (MASK_ONE <<  9)) != 0)
-       value09 /= value;
-
-      if ((mask & (MASK_ONE << 10)) != 0)
-       value10 /= value;
-
-      if ((mask & (MASK_ONE << 11)) != 0)
-       value11 /= value;
-
-      if ((mask & (MASK_ONE << 12)) != 0)
-       value12 /= value;
-
-      if ((mask & (MASK_ONE << 13)) != 0)
-       value13 /= value;
-
-      if ((mask & (MASK_ONE << 14)) != 0)
-       value14 /= value;
-
-      if ((mask & (MASK_ONE << 15)) != 0)
-       value15 /= value;
-
-      if ((mask & (MASK_ONE << 16)) != 0)
-       value16 /= value;
-
-      if ((mask & (MASK_ONE << 17)) != 0)
-       value17 /= value;
-
-      if ((mask & (MASK_ONE << 18)) != 0)
-       value18 /= value;
-
-      if ((mask & (MASK_ONE << 19)) != 0)
-       value19 /= value;
-
-      if ((mask & (MASK_ONE << 20)) != 0)
-       value20 /= value;
-
-      if ((mask & (MASK_ONE << 21)) != 0)
-       value21 /= value;
-
-      if ((mask & (MASK_ONE << 22)) != 0)
-       value22 /= value;
-
-      if ((mask & (MASK_ONE << 23)) != 0)
-       value23 /= value;
-
-      if ((mask & (MASK_ONE << 24)) != 0)
-       value24 /= value;
-
-      if ((mask & (MASK_ONE << 25)) != 0)
-       value25 /= value;
-
-      if ((mask & (MASK_ONE << 26)) != 0)
-       value26 /= value;
-
-      if ((mask & (MASK_ONE << 27)) != 0)
-       value27 /= value;
-
-      if ((mask & (MASK_ONE << 28)) != 0)
-       value28 /= value;
-
-      if ((mask & (MASK_ONE << 29)) != 0)
-       value29 /= value;
-
-      if ((mask & (MASK_ONE << 30)) != 0)
-       value30 /= value;
-
-      if ((mask & (MASK_ONE << 31)) != 0)
-       value31 /= value;
-
-      if ((mask & (MASK_ONE << 32)) != 0)
-       value32 /= value;
-
-      if ((mask & (MASK_ONE << 33)) != 0)
-       value33 /= value;
-
-      if ((mask & (MASK_ONE << 34)) != 0)
-       value34 /= value;
-
-      if ((mask & (MASK_ONE << 35)) != 0)
-       value35 /= value;
-
-      if ((mask & (MASK_ONE << 36)) != 0)
-       value36 /= value;
-
-      if ((mask & (MASK_ONE << 37)) != 0)
-       value37 /= value;
-
-      if ((mask & (MASK_ONE << 38)) != 0)
-       value38 /= value;
-
-      if ((mask & (MASK_ONE << 39)) != 0)
-       value39 /= value;
-    }
-
-  while ((mask = *eq0_mask++) != 0)
-    {
-      eq0 = 0;
-
-      if ((mask & (MASK_ONE <<  0)) != 0)
-       eq0 |= (value00 == ZERO);
-
-      if ((mask & (MASK_ONE <<  1)) != 0)
-       eq0 |= (value01 == ZERO);
-
-      if ((mask & (MASK_ONE <<  2)) != 0)
-       eq0 |= (value02 == ZERO);
-
-      if ((mask & (MASK_ONE <<  3)) != 0)
-       eq0 |= (value03 == ZERO);
-
-      if ((mask & (MASK_ONE <<  4)) != 0)
-       eq0 |= (value04 == ZERO);
-
-      if ((mask & (MASK_ONE <<  5)) != 0)
-       eq0 |= (value05 == ZERO);
-
-      if ((mask & (MASK_ONE <<  6)) != 0)
-       eq0 |= (value06 == ZERO);
-
-      if ((mask & (MASK_ONE <<  7)) != 0)
-       eq0 |= (value07 == ZERO);
-
-      if ((mask & (MASK_ONE <<  8)) != 0)
-       eq0 |= (value08 == ZERO);
-
-      if ((mask & (MASK_ONE <<  9)) != 0)
-       eq0 |= (value09 == ZERO);
-
-      if ((mask & (MASK_ONE << 10)) != 0)
-       eq0 |= (value10 == ZERO);
-
-      if ((mask & (MASK_ONE << 11)) != 0)
-       eq0 |= (value11 == ZERO);
-
-      if ((mask & (MASK_ONE << 12)) != 0)
-       eq0 |= (value12 == ZERO);
-
-      if ((mask & (MASK_ONE << 13)) != 0)
-       eq0 |= (value13 == ZERO);
-
-      if ((mask & (MASK_ONE << 14)) != 0)
-       eq0 |= (value14 == ZERO);
-
-      if ((mask & (MASK_ONE << 15)) != 0)
-       eq0 |= (value15 == ZERO);
-
-      if ((mask & (MASK_ONE << 16)) != 0)
-       eq0 |= (value16 == ZERO);
-
-      if ((mask & (MASK_ONE << 17)) != 0)
-       eq0 |= (value17 == ZERO);
-
-      if ((mask & (MASK_ONE << 18)) != 0)
-       eq0 |= (value18 == ZERO);
-
-      if ((mask & (MASK_ONE << 19)) != 0)
-       eq0 |= (value19 == ZERO);
-
-      if ((mask & (MASK_ONE << 20)) != 0)
-       eq0 |= (value20 == ZERO);
-
-      if ((mask & (MASK_ONE << 21)) != 0)
-       eq0 |= (value21 == ZERO);
-
-      if ((mask & (MASK_ONE << 22)) != 0)
-       eq0 |= (value22 == ZERO);
-
-      if ((mask & (MASK_ONE << 23)) != 0)
-       eq0 |= (value23 == ZERO);
-
-      if ((mask & (MASK_ONE << 24)) != 0)
-       eq0 |= (value24 == ZERO);
-
-      if ((mask & (MASK_ONE << 25)) != 0)
-       eq0 |= (value25 == ZERO);
-
-      if ((mask & (MASK_ONE << 26)) != 0)
-       eq0 |= (value26 == ZERO);
-
-      if ((mask & (MASK_ONE << 27)) != 0)
-       eq0 |= (value27 == ZERO);
-
-      if ((mask & (MASK_ONE << 28)) != 0)
-       eq0 |= (value28 == ZERO);
-
-      if ((mask & (MASK_ONE << 29)) != 0)
-       eq0 |= (value29 == ZERO);
-
-      if ((mask & (MASK_ONE << 30)) != 0)
-       eq0 |= (value30 == ZERO);
-
-      if ((mask & (MASK_ONE << 31)) != 0)
-       eq0 |= (value31 == ZERO);
-
-      if ((mask & (MASK_ONE << 32)) != 0)
-       eq0 |= (value32 == ZERO);
-
-      if ((mask & (MASK_ONE << 33)) != 0)
-       eq0 |= (value33 == ZERO);
-
-      if ((mask & (MASK_ONE << 34)) != 0)
-       eq0 |= (value34 == ZERO);
-
-      if ((mask & (MASK_ONE << 35)) != 0)
-       eq0 |= (value35 == ZERO);
-
-      if ((mask & (MASK_ONE << 36)) != 0)
-       eq0 |= (value36 == ZERO);
-
-      if ((mask & (MASK_ONE << 37)) != 0)
-       eq0 |= (value37 == ZERO);
-
-      if ((mask & (MASK_ONE << 38)) != 0)
-       eq0 |= (value38 == ZERO);
-
-      if ((mask & (MASK_ONE << 39)) != 0)
-       eq0 |= (value39 == ZERO);
-
-      *eq0_ptr++ = eq0;
-    }
-
-  return (  value00 + value01 + value02 + value03 + value04
-         + value05 + value06 + value07 + value08 + value09
-         + value10 + value11 + value12 + value13 + value14
-         + value15 + value16 + value17 + value18 + value19
-         + value20 + value21 + value22 + value23 + value24
-         + value25 + value26 + value27 + value28 + value29
-         + value30 + value31 + value32 + value33 + value34
-         + value35 + value36 + value37 + value38 + value39);
-}
-
-/* { dg-final { scan-assembler "fadd"     } } */
-/* { dg-final { scan-assembler "fsub"     } } */
-/* { dg-final { scan-assembler "fmul"     } } */
-/* { dg-final { scan-assembler "fdiv"     } } */
-/* { dg-final { scan-assembler "fcmpu"    } } */
-/* { dg-final { scan-assembler "xsadddp"  } } */
-/* { dg-final { scan-assembler "xssubdp"  } } */
-/* { dg-final { scan-assembler "xsmuldp"  } } */
-/* { dg-final { scan-assembler "xsdivdp"  } } */
-/* { dg-final { scan-assembler "xscmpudp" } } */
Index: gcc/testsuite/gcc.target/powerpc/pr78953.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr78953.c  
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr78953.c  
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
 
 #include <altivec.h>
 
@@ -16,4 +16,4 @@ foo (vector int *vp, int *ip)
   ip[4] = vec_extract (v, 0);
 }
 
-/* { dg-final { scan-assembler "xxextractuw\|vextuw\[lr\]x" } } */
+/* { dg-final { scan-assembler {\mxxextractuw\M|\mvextuw[lr]x\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/pr65849-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr65849-2.c        
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr65849-2.c        
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,728 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */
-
-/* Test whether we can enable the -mupper-regs-sf with target pragmas.  Make
-   sure float values are allocated to the Altivec registers as well as the
-   traditional FPR registers.  */
-
-#ifndef TYPE
-#define TYPE float
-#endif
-
-#ifndef MASK_TYPE
-#define MASK_TYPE unsigned long long
-#endif
-
-#define MASK_ONE       ((MASK_TYPE)1)
-#define ZERO           ((TYPE) 0.0)
-
-#pragma GCC target ("upper-regs-sf")
-TYPE
-test_add (const MASK_TYPE *add_mask, const TYPE *add_values,
-         const MASK_TYPE *sub_mask, const TYPE *sub_values,
-         const MASK_TYPE *mul_mask, const TYPE *mul_values,
-         const MASK_TYPE *div_mask, const TYPE *div_values,
-         const MASK_TYPE *eq0_mask, int *eq0_ptr)
-{
-  TYPE value;
-  TYPE value00 = ZERO;
-  TYPE value01 = ZERO;
-  TYPE value02 = ZERO;
-  TYPE value03 = ZERO;
-  TYPE value04 = ZERO;
-  TYPE value05 = ZERO;
-  TYPE value06 = ZERO;
-  TYPE value07 = ZERO;
-  TYPE value08 = ZERO;
-  TYPE value09 = ZERO;
-  TYPE value10 = ZERO;
-  TYPE value11 = ZERO;
-  TYPE value12 = ZERO;
-  TYPE value13 = ZERO;
-  TYPE value14 = ZERO;
-  TYPE value15 = ZERO;
-  TYPE value16 = ZERO;
-  TYPE value17 = ZERO;
-  TYPE value18 = ZERO;
-  TYPE value19 = ZERO;
-  TYPE value20 = ZERO;
-  TYPE value21 = ZERO;
-  TYPE value22 = ZERO;
-  TYPE value23 = ZERO;
-  TYPE value24 = ZERO;
-  TYPE value25 = ZERO;
-  TYPE value26 = ZERO;
-  TYPE value27 = ZERO;
-  TYPE value28 = ZERO;
-  TYPE value29 = ZERO;
-  TYPE value30 = ZERO;
-  TYPE value31 = ZERO;
-  TYPE value32 = ZERO;
-  TYPE value33 = ZERO;
-  TYPE value34 = ZERO;
-  TYPE value35 = ZERO;
-  TYPE value36 = ZERO;
-  TYPE value37 = ZERO;
-  TYPE value38 = ZERO;
-  TYPE value39 = ZERO;
-  MASK_TYPE mask;
-  int eq0;
-
-  while ((mask = *add_mask++) != 0)
-    {
-      value = *add_values++;
-
-      __asm__ (" #reg %0" : "+d" (value));
-
-      if ((mask & (MASK_ONE <<  0)) != 0)
-       value00 += value;
-
-      if ((mask & (MASK_ONE <<  1)) != 0)
-       value01 += value;
-
-      if ((mask & (MASK_ONE <<  2)) != 0)
-       value02 += value;
-
-      if ((mask & (MASK_ONE <<  3)) != 0)
-       value03 += value;
-
-      if ((mask & (MASK_ONE <<  4)) != 0)
-       value04 += value;
-
-      if ((mask & (MASK_ONE <<  5)) != 0)
-       value05 += value;
-
-      if ((mask & (MASK_ONE <<  6)) != 0)
-       value06 += value;
-
-      if ((mask & (MASK_ONE <<  7)) != 0)
-       value07 += value;
-
-      if ((mask & (MASK_ONE <<  8)) != 0)
-       value08 += value;
-
-      if ((mask & (MASK_ONE <<  9)) != 0)
-       value09 += value;
-
-      if ((mask & (MASK_ONE << 10)) != 0)
-       value10 += value;
-
-      if ((mask & (MASK_ONE << 11)) != 0)
-       value11 += value;
-
-      if ((mask & (MASK_ONE << 12)) != 0)
-       value12 += value;
-
-      if ((mask & (MASK_ONE << 13)) != 0)
-       value13 += value;
-
-      if ((mask & (MASK_ONE << 14)) != 0)
-       value14 += value;
-
-      if ((mask & (MASK_ONE << 15)) != 0)
-       value15 += value;
-
-      if ((mask & (MASK_ONE << 16)) != 0)
-       value16 += value;
-
-      if ((mask & (MASK_ONE << 17)) != 0)
-       value17 += value;
-
-      if ((mask & (MASK_ONE << 18)) != 0)
-       value18 += value;
-
-      if ((mask & (MASK_ONE << 19)) != 0)
-       value19 += value;
-
-      if ((mask & (MASK_ONE << 20)) != 0)
-       value20 += value;
-
-      if ((mask & (MASK_ONE << 21)) != 0)
-       value21 += value;
-
-      if ((mask & (MASK_ONE << 22)) != 0)
-       value22 += value;
-
-      if ((mask & (MASK_ONE << 23)) != 0)
-       value23 += value;
-
-      if ((mask & (MASK_ONE << 24)) != 0)
-       value24 += value;
-
-      if ((mask & (MASK_ONE << 25)) != 0)
-       value25 += value;
-
-      if ((mask & (MASK_ONE << 26)) != 0)
-       value26 += value;
-
-      if ((mask & (MASK_ONE << 27)) != 0)
-       value27 += value;
-
-      if ((mask & (MASK_ONE << 28)) != 0)
-       value28 += value;
-
-      if ((mask & (MASK_ONE << 29)) != 0)
-       value29 += value;
-
-      if ((mask & (MASK_ONE << 30)) != 0)
-       value30 += value;
-
-      if ((mask & (MASK_ONE << 31)) != 0)
-       value31 += value;
-
-      if ((mask & (MASK_ONE << 32)) != 0)
-       value32 += value;
-
-      if ((mask & (MASK_ONE << 33)) != 0)
-       value33 += value;
-
-      if ((mask & (MASK_ONE << 34)) != 0)
-       value34 += value;
-
-      if ((mask & (MASK_ONE << 35)) != 0)
-       value35 += value;
-
-      if ((mask & (MASK_ONE << 36)) != 0)
-       value36 += value;
-
-      if ((mask & (MASK_ONE << 37)) != 0)
-       value37 += value;
-
-      if ((mask & (MASK_ONE << 38)) != 0)
-       value38 += value;
-
-      if ((mask & (MASK_ONE << 39)) != 0)
-       value39 += value;
-    }
-
-  while ((mask = *sub_mask++) != 0)
-    {
-      value = *sub_values++;
-
-      __asm__ (" #reg %0" : "+d" (value));
-
-      if ((mask & (MASK_ONE <<  0)) != 0)
-       value00 -= value;
-
-      if ((mask & (MASK_ONE <<  1)) != 0)
-       value01 -= value;
-
-      if ((mask & (MASK_ONE <<  2)) != 0)
-       value02 -= value;
-
-      if ((mask & (MASK_ONE <<  3)) != 0)
-       value03 -= value;
-
-      if ((mask & (MASK_ONE <<  4)) != 0)
-       value04 -= value;
-
-      if ((mask & (MASK_ONE <<  5)) != 0)
-       value05 -= value;
-
-      if ((mask & (MASK_ONE <<  6)) != 0)
-       value06 -= value;
-
-      if ((mask & (MASK_ONE <<  7)) != 0)
-       value07 -= value;
-
-      if ((mask & (MASK_ONE <<  8)) != 0)
-       value08 -= value;
-
-      if ((mask & (MASK_ONE <<  9)) != 0)
-       value09 -= value;
-
-      if ((mask & (MASK_ONE << 10)) != 0)
-       value10 -= value;
-
-      if ((mask & (MASK_ONE << 11)) != 0)
-       value11 -= value;
-
-      if ((mask & (MASK_ONE << 12)) != 0)
-       value12 -= value;
-
-      if ((mask & (MASK_ONE << 13)) != 0)
-       value13 -= value;
-
-      if ((mask & (MASK_ONE << 14)) != 0)
-       value14 -= value;
-
-      if ((mask & (MASK_ONE << 15)) != 0)
-       value15 -= value;
-
-      if ((mask & (MASK_ONE << 16)) != 0)
-       value16 -= value;
-
-      if ((mask & (MASK_ONE << 17)) != 0)
-       value17 -= value;
-
-      if ((mask & (MASK_ONE << 18)) != 0)
-       value18 -= value;
-
-      if ((mask & (MASK_ONE << 19)) != 0)
-       value19 -= value;
-
-      if ((mask & (MASK_ONE << 20)) != 0)
-       value20 -= value;
-
-      if ((mask & (MASK_ONE << 21)) != 0)
-       value21 -= value;
-
-      if ((mask & (MASK_ONE << 22)) != 0)
-       value22 -= value;
-
-      if ((mask & (MASK_ONE << 23)) != 0)
-       value23 -= value;
-
-      if ((mask & (MASK_ONE << 24)) != 0)
-       value24 -= value;
-
-      if ((mask & (MASK_ONE << 25)) != 0)
-       value25 -= value;
-
-      if ((mask & (MASK_ONE << 26)) != 0)
-       value26 -= value;
-
-      if ((mask & (MASK_ONE << 27)) != 0)
-       value27 -= value;
-
-      if ((mask & (MASK_ONE << 28)) != 0)
-       value28 -= value;
-
-      if ((mask & (MASK_ONE << 29)) != 0)
-       value29 -= value;
-
-      if ((mask & (MASK_ONE << 30)) != 0)
-       value30 -= value;
-
-      if ((mask & (MASK_ONE << 31)) != 0)
-       value31 -= value;
-
-      if ((mask & (MASK_ONE << 32)) != 0)
-       value32 -= value;
-
-      if ((mask & (MASK_ONE << 33)) != 0)
-       value33 -= value;
-
-      if ((mask & (MASK_ONE << 34)) != 0)
-       value34 -= value;
-
-      if ((mask & (MASK_ONE << 35)) != 0)
-       value35 -= value;
-
-      if ((mask & (MASK_ONE << 36)) != 0)
-       value36 -= value;
-
-      if ((mask & (MASK_ONE << 37)) != 0)
-       value37 -= value;
-
-      if ((mask & (MASK_ONE << 38)) != 0)
-       value38 -= value;
-
-      if ((mask & (MASK_ONE << 39)) != 0)
-       value39 -= value;
-    }
-
-  while ((mask = *mul_mask++) != 0)
-    {
-      value = *mul_values++;
-
-      __asm__ (" #reg %0" : "+d" (value));
-
-      if ((mask & (MASK_ONE <<  0)) != 0)
-       value00 *= value;
-
-      if ((mask & (MASK_ONE <<  1)) != 0)
-       value01 *= value;
-
-      if ((mask & (MASK_ONE <<  2)) != 0)
-       value02 *= value;
-
-      if ((mask & (MASK_ONE <<  3)) != 0)
-       value03 *= value;
-
-      if ((mask & (MASK_ONE <<  4)) != 0)
-       value04 *= value;
-
-      if ((mask & (MASK_ONE <<  5)) != 0)
-       value05 *= value;
-
-      if ((mask & (MASK_ONE <<  6)) != 0)
-       value06 *= value;
-
-      if ((mask & (MASK_ONE <<  7)) != 0)
-       value07 *= value;
-
-      if ((mask & (MASK_ONE <<  8)) != 0)
-       value08 *= value;
-
-      if ((mask & (MASK_ONE <<  9)) != 0)
-       value09 *= value;
-
-      if ((mask & (MASK_ONE << 10)) != 0)
-       value10 *= value;
-
-      if ((mask & (MASK_ONE << 11)) != 0)
-       value11 *= value;
-
-      if ((mask & (MASK_ONE << 12)) != 0)
-       value12 *= value;
-
-      if ((mask & (MASK_ONE << 13)) != 0)
-       value13 *= value;
-
-      if ((mask & (MASK_ONE << 14)) != 0)
-       value14 *= value;
-
-      if ((mask & (MASK_ONE << 15)) != 0)
-       value15 *= value;
-
-      if ((mask & (MASK_ONE << 16)) != 0)
-       value16 *= value;
-
-      if ((mask & (MASK_ONE << 17)) != 0)
-       value17 *= value;
-
-      if ((mask & (MASK_ONE << 18)) != 0)
-       value18 *= value;
-
-      if ((mask & (MASK_ONE << 19)) != 0)
-       value19 *= value;
-
-      if ((mask & (MASK_ONE << 20)) != 0)
-       value20 *= value;
-
-      if ((mask & (MASK_ONE << 21)) != 0)
-       value21 *= value;
-
-      if ((mask & (MASK_ONE << 22)) != 0)
-       value22 *= value;
-
-      if ((mask & (MASK_ONE << 23)) != 0)
-       value23 *= value;
-
-      if ((mask & (MASK_ONE << 24)) != 0)
-       value24 *= value;
-
-      if ((mask & (MASK_ONE << 25)) != 0)
-       value25 *= value;
-
-      if ((mask & (MASK_ONE << 26)) != 0)
-       value26 *= value;
-
-      if ((mask & (MASK_ONE << 27)) != 0)
-       value27 *= value;
-
-      if ((mask & (MASK_ONE << 28)) != 0)
-       value28 *= value;
-
-      if ((mask & (MASK_ONE << 29)) != 0)
-       value29 *= value;
-
-      if ((mask & (MASK_ONE << 30)) != 0)
-       value30 *= value;
-
-      if ((mask & (MASK_ONE << 31)) != 0)
-       value31 *= value;
-
-      if ((mask & (MASK_ONE << 32)) != 0)
-       value32 *= value;
-
-      if ((mask & (MASK_ONE << 33)) != 0)
-       value33 *= value;
-
-      if ((mask & (MASK_ONE << 34)) != 0)
-       value34 *= value;
-
-      if ((mask & (MASK_ONE << 35)) != 0)
-       value35 *= value;
-
-      if ((mask & (MASK_ONE << 36)) != 0)
-       value36 *= value;
-
-      if ((mask & (MASK_ONE << 37)) != 0)
-       value37 *= value;
-
-      if ((mask & (MASK_ONE << 38)) != 0)
-       value38 *= value;
-
-      if ((mask & (MASK_ONE << 39)) != 0)
-       value39 *= value;
-    }
-
-  while ((mask = *div_mask++) != 0)
-    {
-      value = *div_values++;
-
-      __asm__ (" #reg %0" : "+d" (value));
-
-      if ((mask & (MASK_ONE <<  0)) != 0)
-       value00 /= value;
-
-      if ((mask & (MASK_ONE <<  1)) != 0)
-       value01 /= value;
-
-      if ((mask & (MASK_ONE <<  2)) != 0)
-       value02 /= value;
-
-      if ((mask & (MASK_ONE <<  3)) != 0)
-       value03 /= value;
-
-      if ((mask & (MASK_ONE <<  4)) != 0)
-       value04 /= value;
-
-      if ((mask & (MASK_ONE <<  5)) != 0)
-       value05 /= value;
-
-      if ((mask & (MASK_ONE <<  6)) != 0)
-       value06 /= value;
-
-      if ((mask & (MASK_ONE <<  7)) != 0)
-       value07 /= value;
-
-      if ((mask & (MASK_ONE <<  8)) != 0)
-       value08 /= value;
-
-      if ((mask & (MASK_ONE <<  9)) != 0)
-       value09 /= value;
-
-      if ((mask & (MASK_ONE << 10)) != 0)
-       value10 /= value;
-
-      if ((mask & (MASK_ONE << 11)) != 0)
-       value11 /= value;
-
-      if ((mask & (MASK_ONE << 12)) != 0)
-       value12 /= value;
-
-      if ((mask & (MASK_ONE << 13)) != 0)
-       value13 /= value;
-
-      if ((mask & (MASK_ONE << 14)) != 0)
-       value14 /= value;
-
-      if ((mask & (MASK_ONE << 15)) != 0)
-       value15 /= value;
-
-      if ((mask & (MASK_ONE << 16)) != 0)
-       value16 /= value;
-
-      if ((mask & (MASK_ONE << 17)) != 0)
-       value17 /= value;
-
-      if ((mask & (MASK_ONE << 18)) != 0)
-       value18 /= value;
-
-      if ((mask & (MASK_ONE << 19)) != 0)
-       value19 /= value;
-
-      if ((mask & (MASK_ONE << 20)) != 0)
-       value20 /= value;
-
-      if ((mask & (MASK_ONE << 21)) != 0)
-       value21 /= value;
-
-      if ((mask & (MASK_ONE << 22)) != 0)
-       value22 /= value;
-
-      if ((mask & (MASK_ONE << 23)) != 0)
-       value23 /= value;
-
-      if ((mask & (MASK_ONE << 24)) != 0)
-       value24 /= value;
-
-      if ((mask & (MASK_ONE << 25)) != 0)
-       value25 /= value;
-
-      if ((mask & (MASK_ONE << 26)) != 0)
-       value26 /= value;
-
-      if ((mask & (MASK_ONE << 27)) != 0)
-       value27 /= value;
-
-      if ((mask & (MASK_ONE << 28)) != 0)
-       value28 /= value;
-
-      if ((mask & (MASK_ONE << 29)) != 0)
-       value29 /= value;
-
-      if ((mask & (MASK_ONE << 30)) != 0)
-       value30 /= value;
-
-      if ((mask & (MASK_ONE << 31)) != 0)
-       value31 /= value;
-
-      if ((mask & (MASK_ONE << 32)) != 0)
-       value32 /= value;
-
-      if ((mask & (MASK_ONE << 33)) != 0)
-       value33 /= value;
-
-      if ((mask & (MASK_ONE << 34)) != 0)
-       value34 /= value;
-
-      if ((mask & (MASK_ONE << 35)) != 0)
-       value35 /= value;
-
-      if ((mask & (MASK_ONE << 36)) != 0)
-       value36 /= value;
-
-      if ((mask & (MASK_ONE << 37)) != 0)
-       value37 /= value;
-
-      if ((mask & (MASK_ONE << 38)) != 0)
-       value38 /= value;
-
-      if ((mask & (MASK_ONE << 39)) != 0)
-       value39 /= value;
-    }
-
-  while ((mask = *eq0_mask++) != 0)
-    {
-      eq0 = 0;
-
-      if ((mask & (MASK_ONE <<  0)) != 0)
-       eq0 |= (value00 == ZERO);
-
-      if ((mask & (MASK_ONE <<  1)) != 0)
-       eq0 |= (value01 == ZERO);
-
-      if ((mask & (MASK_ONE <<  2)) != 0)
-       eq0 |= (value02 == ZERO);
-
-      if ((mask & (MASK_ONE <<  3)) != 0)
-       eq0 |= (value03 == ZERO);
-
-      if ((mask & (MASK_ONE <<  4)) != 0)
-       eq0 |= (value04 == ZERO);
-
-      if ((mask & (MASK_ONE <<  5)) != 0)
-       eq0 |= (value05 == ZERO);
-
-      if ((mask & (MASK_ONE <<  6)) != 0)
-       eq0 |= (value06 == ZERO);
-
-      if ((mask & (MASK_ONE <<  7)) != 0)
-       eq0 |= (value07 == ZERO);
-
-      if ((mask & (MASK_ONE <<  8)) != 0)
-       eq0 |= (value08 == ZERO);
-
-      if ((mask & (MASK_ONE <<  9)) != 0)
-       eq0 |= (value09 == ZERO);
-
-      if ((mask & (MASK_ONE << 10)) != 0)
-       eq0 |= (value10 == ZERO);
-
-      if ((mask & (MASK_ONE << 11)) != 0)
-       eq0 |= (value11 == ZERO);
-
-      if ((mask & (MASK_ONE << 12)) != 0)
-       eq0 |= (value12 == ZERO);
-
-      if ((mask & (MASK_ONE << 13)) != 0)
-       eq0 |= (value13 == ZERO);
-
-      if ((mask & (MASK_ONE << 14)) != 0)
-       eq0 |= (value14 == ZERO);
-
-      if ((mask & (MASK_ONE << 15)) != 0)
-       eq0 |= (value15 == ZERO);
-
-      if ((mask & (MASK_ONE << 16)) != 0)
-       eq0 |= (value16 == ZERO);
-
-      if ((mask & (MASK_ONE << 17)) != 0)
-       eq0 |= (value17 == ZERO);
-
-      if ((mask & (MASK_ONE << 18)) != 0)
-       eq0 |= (value18 == ZERO);
-
-      if ((mask & (MASK_ONE << 19)) != 0)
-       eq0 |= (value19 == ZERO);
-
-      if ((mask & (MASK_ONE << 20)) != 0)
-       eq0 |= (value20 == ZERO);
-
-      if ((mask & (MASK_ONE << 21)) != 0)
-       eq0 |= (value21 == ZERO);
-
-      if ((mask & (MASK_ONE << 22)) != 0)
-       eq0 |= (value22 == ZERO);
-
-      if ((mask & (MASK_ONE << 23)) != 0)
-       eq0 |= (value23 == ZERO);
-
-      if ((mask & (MASK_ONE << 24)) != 0)
-       eq0 |= (value24 == ZERO);
-
-      if ((mask & (MASK_ONE << 25)) != 0)
-       eq0 |= (value25 == ZERO);
-
-      if ((mask & (MASK_ONE << 26)) != 0)
-       eq0 |= (value26 == ZERO);
-
-      if ((mask & (MASK_ONE << 27)) != 0)
-       eq0 |= (value27 == ZERO);
-
-      if ((mask & (MASK_ONE << 28)) != 0)
-       eq0 |= (value28 == ZERO);
-
-      if ((mask & (MASK_ONE << 29)) != 0)
-       eq0 |= (value29 == ZERO);
-
-      if ((mask & (MASK_ONE << 30)) != 0)
-       eq0 |= (value30 == ZERO);
-
-      if ((mask & (MASK_ONE << 31)) != 0)
-       eq0 |= (value31 == ZERO);
-
-      if ((mask & (MASK_ONE << 32)) != 0)
-       eq0 |= (value32 == ZERO);
-
-      if ((mask & (MASK_ONE << 33)) != 0)
-       eq0 |= (value33 == ZERO);
-
-      if ((mask & (MASK_ONE << 34)) != 0)
-       eq0 |= (value34 == ZERO);
-
-      if ((mask & (MASK_ONE << 35)) != 0)
-       eq0 |= (value35 == ZERO);
-
-      if ((mask & (MASK_ONE << 36)) != 0)
-       eq0 |= (value36 == ZERO);
-
-      if ((mask & (MASK_ONE << 37)) != 0)
-       eq0 |= (value37 == ZERO);
-
-      if ((mask & (MASK_ONE << 38)) != 0)
-       eq0 |= (value38 == ZERO);
-
-      if ((mask & (MASK_ONE << 39)) != 0)
-       eq0 |= (value39 == ZERO);
-
-      *eq0_ptr++ = eq0;
-    }
-
-  return (  value00 + value01 + value02 + value03 + value04
-         + value05 + value06 + value07 + value08 + value09
-         + value10 + value11 + value12 + value13 + value14
-         + value15 + value16 + value17 + value18 + value19
-         + value20 + value21 + value22 + value23 + value24
-         + value25 + value26 + value27 + value28 + value29
-         + value30 + value31 + value32 + value33 + value34
-         + value35 + value36 + value37 + value38 + value39);
-}
-
-/* { dg-final { scan-assembler "fadds"     } } */
-/* { dg-final { scan-assembler "fsubs"     } } */
-/* { dg-final { scan-assembler "fmuls"     } } */
-/* { dg-final { scan-assembler "fdivs"     } } */
-/* { dg-final { scan-assembler "fcmpu"    } } */
-/* { dg-final { scan-assembler "xsaddsp"  } } */
-/* { dg-final { scan-assembler "xssubsp"  } } */
-/* { dg-final { scan-assembler "xsmulsp"  } } */
-/* { dg-final { scan-assembler "xsdivsp"  } } */
-/* { dg-final { scan-assembler "xscmpudp" } } */
Index: gcc/testsuite/gcc.target/powerpc/ppc-round.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-round.c        
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/ppc-round.c        
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -2,15 +2,15 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power7" } } */
-/* { dg-options "-O2 -mcpu=power7 -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "stfiwx" 4 } } */
-/* { dg-final { scan-assembler-times "lfiwax" 2 } } */
-/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */
-/* { dg-final { scan-assembler-times "fctiwz " 2 } } */
-/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */
-/* { dg-final { scan-assembler-times "fcfids " 2 } } */
-/* { dg-final { scan-assembler-not "lwz" } } */
-/* { dg-final { scan-assembler-not "stw" } } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M}     4 } } */
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M}     2 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M}     2 } } */
+/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M}   2 } } */
+/* { dg-final { scan-assembler-not   {\mlwz\M}                      } } */
+/* { dg-final { scan-assembler-not   {\mstw\M}                      } } */
 
 /* Make sure we don't have loads/stores to the GPR unit.  */
 double
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c    
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c    
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -2,8 +2,8 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power7" } } */
-/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler "friz" } } */
+/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler {\mfriz\M|\mxsrdpiz\M} } } */
 
 double round_double_llong (double a)
 {
Index: gcc/testsuite/gcc.target/powerpc/vec-set-int.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-set-int.c      
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-set-int.c      
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -3,7 +3,7 @@
 /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
 
 vector int
 insert_0_0 (vector int v)
Index: gcc/testsuite/gcc.target/powerpc/pr71720.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr71720.c  
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr71720.c  
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
 
 /* Verify that we generate xxspltw <reg>,<reg>,0 for V4SFmode splat.  */
 
Index: gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c   
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c   
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,7 +1,7 @@
 /* { dg-do run { target { powerpc64*-*-* && { lp64 && p9vector_hw } } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
 
 #include <altivec.h> // vector
 
Index: gcc/testsuite/gcc.target/powerpc/vec-init-3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-init-3.c       
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-init-3.c       
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
 
 vector long
 merge (long a, long b)
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c     
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c     
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -2,15 +2,13 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power7" } } */
-/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "lfiwax" 2 } } */
-/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */
-/* { dg-final { scan-assembler-times "fcfids " 3 } } */
-/* { dg-final { scan-assembler-times "fcfidus " 1 } } */
-/* { dg-final { scan-assembler-times "fcfid " 3 } } */
-/* { dg-final { scan-assembler-times "fcfidu " 1 } } */
-/* { dg-final { scan-assembler-not "xscvdpsxds" } } */
-/* { dg-final { scan-assembler-not "xscvdpuxds" } } */
+/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M}  3 } } */
+/* { dg-final { scan-assembler-times {\mfcfidus\M|\mxscvuxdsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M}   3 } } */
+/* { dg-final { scan-assembler-times {\mfcfidu\M|\mxscvuxddp\M}  1 } } */
 
 void int_to_float (float *dest, int *src)
 {
Index: gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c    
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c    
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */
+/* { dg-options "-mcpu=power8 -O2" } */
 
 float
 load_store_sf (unsigned long num,
Index: gcc/testsuite/gcc.target/powerpc/vec-set-char.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-set-char.c     
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-set-char.c     
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -3,7 +3,7 @@
 /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
 
 vector char
 insert_0_0 (vector char v)
Index: gcc/testsuite/gcc.target/powerpc/vec-extract-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-extract-1.c    
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-extract-1.c    
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-di" } */
+/* { dg-options "-mcpu=power8 -O2" } */
 
 #include <altivec.h>
 
Index: gcc/testsuite/gcc.target/powerpc/upper-regs-df.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/upper-regs-df.c    
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/upper-regs-df.c    
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -2,10 +2,10 @@
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
-/* { dg-options "-mcpu=power7 -O2 -mupper-regs-df" } */
+/* { dg-options "-mcpu=power7 -O2" } */
 
-/* Test for the -mupper-regs-df option to make sure double values are allocated
-   to the Altivec registers as well as the traditional FPR registers.  */
+/* Test to make sure double values are allocated to the Altivec registers as
+   well as the traditional FPR registers.  */
 
 #ifndef TYPE
 #define TYPE double
Index: gcc/testsuite/gcc.target/powerpc/vec-init-6.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-init-6.c       
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-init-6.c       
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power8 -O2" } */
 
 vector int
 merge (int a, int b, int c, int d)
Index: gcc/testsuite/gcc.target/powerpc/vec-init-7.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-init-7.c       
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-init-7.c       
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power8" } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power8 -O2" } */
 
 vector int
 splat (int a)
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c     
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c     
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -2,13 +2,11 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power7" } } */
-/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "fctiwz " 2 } } */
-/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */
-/* { dg-final { scan-assembler-times "fctidz " 2 } } */
-/* { dg-final { scan-assembler-times "fctiduz " 2 } } */
-/* { dg-final { scan-assembler-not "xscvdpsxds" } } */
-/* { dg-final { scan-assembler-not "xscvdpuxds" } } */
+/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mfctiduz\M|\mxscvdpuxds\M} 2 } } */
 
 void float_to_int  (int *dest, float  src) { *dest = (int) src; }
 void double_to_int (int *dest, double src) { *dest = (int) src; }
Index: gcc/testsuite/gcc.target/powerpc/vec-set-short.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-set-short.c    
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
     (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-set-short.c    
(.../gcc/testsuite/gcc.target/powerpc)  (working copy)
@@ -3,7 +3,7 @@
 /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
 
 vector short
 insert_0_0 (vector short v)

[PATCH, cleanup] Remove PowerPC -mupper-regs-* options

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