Hi,
Kostik Belousov wrote:
On Mon, Dec 31, 2007 at 05:38:43PM +0800, Erich Dollansky wrote:
Kostik Belousov wrote:
On Sat, Dec 29, 2007 at 01:12:04PM +0200, Kostik Belousov wrote:
On Sat, Dec 29, 2007 at 12:14:11AM -0800, Kip Macy wrote:
I.e., it seems that gcc does not feel too guilty generating unaligned
half-word writes on i386. :(
this should not be a problem inside a cache line.
If the access goes accross two cache lines and the other cache line is
not in the cache, it becomes real difficult.
I can't tell you what the hardware actually does in this case.
It should read the second affected cache line into the cache. But what
happens if the second affected cache line is blocked by another CPU
while the current CPU blocks the first cache line?
From the manual, 253668, 7.1.1:
I think we might get any half of the operation as a result.
so, both CPUs are blocked as none can access the other cache line.
Is there really nothing in a normal PC to handle this?
I do not know. The hardware I developed earlier was able to handle this
by aborting both bus cycles.
It was then task of the operating system to handle this.
Erich
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