Hi,
Kostik Belousov wrote:
On Sat, Dec 29, 2007 at 01:12:04PM +0200, Kostik Belousov wrote:
On Sat, Dec 29, 2007 at 12:14:11AM -0800, Kip Macy wrote:
I.e., it seems that gcc does not feel too guilty generating unaligned
half-word writes on i386. :(
this should not be a problem inside a cache line.
If the access goes accross two cache lines and the other cache line is
not in the cache, it becomes real difficult.
I can't tell you what the hardware actually does in this case.
It should read the second affected cache line into the cache. But what
happens if the second affected cache line is blocked by another CPU
while the current CPU blocks the first cache line?
Erich
_______________________________________________
freebsd-hackers@freebsd.org mailing list
http://lists.freebsd.org/mailman/listinfo/freebsd-hackers
To unsubscribe, send any mail to "[EMAIL PROTECTED]"
