On Sat, Dec 29, 2007 at 06:03:15PM +0800, Erich Dollansky wrote: >All RISC based designs need the alignment so that the CPU can fetch a CPU >word in one go. CISC based designs do not have this limitiation.
It's more that the additional logic required to split a single memory operation (load/store) into multiple bus cycles is incompatible with the RISC philosophy (though the AMD29K could apparently generate dummy bus cycles to limit the number of bit transitions on any cycle to reduce the I/O load). Most CISC architectures either needed to support non-aligned accesses for compatibility with previous architectures (eg 8080->8086) or gained non-aligned access support when they were enhanced to support wider buses (eg M68K). >I also do not know of any other CISC based design which made it to >mainstream. You might like to read http://jbayko.sasktelwebsite.net/cpu.html -- Peter Jeremy Please excuse any delays as the result of my ISP's inability to implement an MTA that is either RFC2821-compliant or matches their claimed behaviour.
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