On Mon, Dec 31, 2007 at 05:38:43PM +0800, Erich Dollansky wrote: > Hi, > > Kostik Belousov wrote: > >On Sat, Dec 29, 2007 at 01:12:04PM +0200, Kostik Belousov wrote: > >>On Sat, Dec 29, 2007 at 12:14:11AM -0800, Kip Macy wrote: > > > >I.e., it seems that gcc does not feel too guilty generating unaligned > >half-word writes on i386. :( > > this should not be a problem inside a cache line. > > If the access goes accross two cache lines and the other cache line is > not in the cache, it becomes real difficult. > > I can't tell you what the hardware actually does in this case. > > It should read the second affected cache line into the cache. But what > happens if the second affected cache line is blocked by another CPU > while the current CPU blocks the first cache line?
From the manual, 253668, 7.1.1: Accesses to cacheable memory that are split across bus widths, cache lines, and page boundaries are not guaranteed to be atomic by the Intel Core 2 Duo, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The Intel Core 2 Duo, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, and P6 family processors provide bus control signals that permit external memory subsystems to make split accesses atomic; however, nonaligned data accesses will seriously impact the performance of the processor and should be avoided. I think we might get any half of the operation as a result.
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