Just some feedback... I added the two-stage synchronizer + filter (as suggested by Jan de Kruyf - solution at page 13) to the fpga input pins. First a filtered only the quad signals, and I was still receiving glitches. Than I added the same filter also to the epp interface, and after that the glitches were gone :)
Regardrs, Klemen ________________________________ From: Peter C. Wallace <[email protected]> To: Klemen Dovrtel <[email protected]>; Enhanced Machine Controller (EMC) <[email protected]> Sent: Saturday, March 2, 2013 9:58 PM Subject: Re: [Emc-users] fpga epp data transfer - strange behaviour On Sat, 2 Mar 2013, Klemen Dovrtel wrote: > Date: Sat, 2 Mar 2013 10:57:52 -0800 (PST) > From: Klemen Dovrtel <[email protected]> > To: "Enhanced Machine Controller (EMC)" <[email protected]> > Subject: Re: [Emc-users] fpga epp data transfer - strange behaviour > > I see, if i understand this correctly, i should add a two-stage synchronizer > to latch the data from QuadA/B before sampling with counter logic? Yes or a digital filter (or at least fix the double sampling of asynchronous data even though the synthesizer _may_ optimize it away) > > Ok, thank you for the suggestions, i will try to add some filters, as > suggested also by Jan de Kruyf. > > Regards, Klemen > > Peter Wallace Mesa Electronics (\__/) (='.'=) This is Bunny. Copy and paste bunny into your (")_(") signature to help him gain world domination. ------------------------------------------------------------------------------ Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_feb _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
