On Sat, 2 Mar 2013, Klemen Dovrtel wrote:
> Date: Sat, 2 Mar 2013 10:57:52 -0800 (PST)
> From: Klemen Dovrtel <[email protected]>
> To: "Enhanced Machine Controller (EMC)" <[email protected]>
> Subject: Re: [Emc-users] fpga epp data transfer - strange behaviour
>
> I see, if i understand this correctly, i should add a two-stage synchronizer
> to latch the data from QuadA/B before sampling with counter logic?
Yes or a digital filter (or at least fix the double sampling of
asynchronous data even though the synthesizer _may_ optimize it away)
>
> Ok, thank you for the suggestions, i will try to add some filters, as
> suggested also by Jan de Kruyf.
>
> Regards, Klemen
>
>
Peter Wallace
Mesa Electronics
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