Hi All, > -----Original Message----- > From: Biju <[email protected]> > Sent: 29 July 2026 13:55 > Subject: [PATCH v2 01/16] dt-bindings: display: bridge: renesas,dsi: Document > RZ/G3L > > From: Biju Das <[email protected]> > > The RZ/G3L DSI IP is similar to the RZ/G2L but has different global PHY > timings and also the PLLCLK is > ungateble clock. Add the compatible string "renesas,r9a08g046-mipi-dsi" to > handle these difference for > the Renesas RZ/G3L SoC. The power to DSI region is controlled by SYSC block. > Document renesas,sysc-pwrrdy property to handle the power control. > > Signed-off-by: Biju Das <[email protected]> > --- > v1->v2: > * Dropped renesas,sysc-pwrrdy property as it is modelled as power > sequence. > --- > .../devicetree/bindings/display/bridge/renesas,dsi.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > index c20625b8425e..3832a553871b 100644 > --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > @@ -28,6 +28,7 @@ properties: > - const: renesas,r9a09g057-mipi-dsi > > - enum: > + - renesas,r9a08g046-mipi-dsi # RZ/G3L > - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) > > reg: > -- > 2.43.0
Applied to drm-misc-next as the compatible used in power/sequence driver and also, for easy rebase for the RZ/G3E DU series. Cheers, Biju
