RE: [PATCH v2 08/16] drm: renesas: rz-du: Add RZ/G3L (R9A08G046) DU support

[Biju Das]

Hi Tommaso Merci,

Thanks for the feedback.

> -----Original Message-----
> From: Tommaso Merciai <tommaso.merciai...@bp.renesas.com>
> Sent: 05 August 2026 15:55
> Subject: Re: [PATCH v2 08/16] drm: renesas: rz-du: Add RZ/G3L (R9A08G046) DU 
> support
> 
> Hi Biju,
> Thanks for your patch.
> 
> On Wed, Jul 29, 2026 at 01:55:00PM +0100, Biju wrote:
> > From: Biju Das <biju.das...@bp.renesas.com>
> >
> > Add Display Unit support for the Renesas RZ/G3L SoC (R9A08G046). It is
> > similar to the one found on RZ/G2L, but has LVDS support.
> >
> > Signed-off-by: Biju Das <biju.das...@bp.renesas.com>
> > ---
> > v1->v2:
> >  * Dropped the macro RZG2L_DU_FEATURE_SMUX2_DSI_CLK and RZG2L_DU_MAX_LVDS.
> >  * Dropped the variable rcdu from struct rzg2l_du_encoder.
> >  * Dropped the variable lvds from struct rzg2l_du_device.
> > ---
> >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 22
> > +++++++++++++++++++-  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h |
> > 1 +
> >  2 files changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > index 3d13f61d3c97..a8d841421a0b 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > @@ -55,6 +55,24 @@ static const struct rzg2l_du_device_info 
> > rzg2l_du_r9a07g044_info = {
> >     .mode_clock_max = 83500,
> >  };
> >
> > +static const struct rzg2l_du_device_info rzg2l_du_r9a08g046_info = {
> > +   .channels_mask = BIT(0),
> > +   .routes = {
> > +           [RZG2L_DU_OUTPUT_DSI0] = {
> > +                   .possible_outputs = BIT(0),
> > +                   .port = 0,
> > +           },
> > +           [RZG2L_DU_OUTPUT_DPAD0] = {
> > +                   .possible_outputs = BIT(0),
> > +                   .port = 1,
> > +           },
> > +           [RZG2L_DU_OUTPUT_LVDS0] = {
> > +                   .possible_outputs = BIT(0),
> > +                   .port = 2,
> > +           },
> > +   },
> > +};
> 
> rzg2l_du_r9a08g046_info declares RZG2L_DU_OUTPUT_DPAD0 route but we are not 
> specifying
> mode_clock_min/mode_clock_max so
> rzg2l_du_encoder_mode_valid() returns MODE_CLOCK_HIGH for every mode on the
> RZG2L_DU_OUTPUT_DPAD0 output.
> 
> Please correct me if I'm wrong.

I just added the definitions based on the ports mentioned in the bindings.

I haven't tested DPI mode, that is the reason for not adding 
mode_clock_min/mode_clock_max here.

Cheers,
Biju