Hi Biju,
Thanks for your patch.
On Wed, Jul 29, 2026 at 01:55:00PM +0100, Biju wrote:
> From: Biju Das <[email protected]>
>
> Add Display Unit support for the Renesas RZ/G3L SoC (R9A08G046). It is
> similar to the one found on RZ/G2L, but has LVDS support.
>
> Signed-off-by: Biju Das <[email protected]>
> ---
> v1->v2:
> * Dropped the macro RZG2L_DU_FEATURE_SMUX2_DSI_CLK and RZG2L_DU_MAX_LVDS.
> * Dropped the variable rcdu from struct rzg2l_du_encoder.
> * Dropped the variable lvds from struct rzg2l_du_device.
> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 22 +++++++++++++++++++-
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 1 +
> 2 files changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> index 3d13f61d3c97..a8d841421a0b 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> @@ -55,6 +55,24 @@ static const struct rzg2l_du_device_info
> rzg2l_du_r9a07g044_info = {
> .mode_clock_max = 83500,
> };
>
> +static const struct rzg2l_du_device_info rzg2l_du_r9a08g046_info = {
> + .channels_mask = BIT(0),
> + .routes = {
> + [RZG2L_DU_OUTPUT_DSI0] = {
> + .possible_outputs = BIT(0),
> + .port = 0,
> + },
> + [RZG2L_DU_OUTPUT_DPAD0] = {
> + .possible_outputs = BIT(0),
> + .port = 1,
> + },
> + [RZG2L_DU_OUTPUT_LVDS0] = {
> + .possible_outputs = BIT(0),
> + .port = 2,
> + },
> + },
> +};
rzg2l_du_r9a08g046_info declares RZG2L_DU_OUTPUT_DPAD0 route but we are
not specifying mode_clock_min/mode_clock_max so
rzg2l_du_encoder_mode_valid() returns MODE_CLOCK_HIGH for every mode on the
RZG2L_DU_OUTPUT_DPAD0 output.
Please correct me if I'm wrong.
Kind regards,
Tommaso
> +
> static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = {
> .channels_mask = BIT(0),
> .routes = {
> @@ -81,6 +99,7 @@ static const struct rzg2l_du_device_info
> rzg2l_du_r9a09g077_info = {
> static const struct of_device_id rzg2l_du_of_table[] = {
> { .compatible = "renesas,r9a07g043u-du", .data =
> &rzg2l_du_r9a07g043u_info },
> { .compatible = "renesas,r9a07g044-du", .data =
> &rzg2l_du_r9a07g044_info },
> + { .compatible = "renesas,r9a08g046-du", .data =
> &rzg2l_du_r9a08g046_info },
> { .compatible = "renesas,r9a09g057-du", .data =
> &rzg2l_du_r9a09g057_info },
> { .compatible = "renesas,r9a09g077-du", .data =
> &rzg2l_du_r9a09g077_info },
> { /* sentinel */ }
> @@ -92,7 +111,8 @@ const char *rzg2l_du_output_name(enum rzg2l_du_output
> output)
> {
> static const char * const names[] = {
> [RZG2L_DU_OUTPUT_DSI0] = "DSI0",
> - [RZG2L_DU_OUTPUT_DPAD0] = "DPAD0"
> + [RZG2L_DU_OUTPUT_DPAD0] = "DPAD0",
> + [RZG2L_DU_OUTPUT_LVDS0] = "LVDS0"
> };
>
> if (output >= ARRAY_SIZE(names))
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> index baf076d69cda..7812f36edbe0 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> @@ -25,6 +25,7 @@ struct drm_property;
> enum rzg2l_du_output {
> RZG2L_DU_OUTPUT_DSI0,
> RZG2L_DU_OUTPUT_DPAD0,
> + RZG2L_DU_OUTPUT_LVDS0,
> RZG2L_DU_OUTPUT_MAX,
> };
>
> --
> 2.43.0
>
