On Wed, Jul 29, 2026 at 01:54:55PM +0100, Biju wrote: > From: Biju Das <[email protected]> > > Move the post-reset activation delay into the hw_info structure as > activation_dly, allowing SoC-specific values to be defined per > compatible. This prepares the driver for supporting SoCs that require a > different delay after reset deassertion. >
Reviewed-by: Tommaso Merciai <[email protected]> Kind Regards, Tommaso > Signed-off-by: Biju Das <[email protected]> > --- > v1->v2: > * No change. > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > index 2128fd16ebc9..1538eeece2b5 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -59,6 +59,7 @@ struct rzg2l_mipi_dsi_hw_info { > u32 dphyctrl0_init_val; > unsigned long min_dclk; > unsigned long max_dclk; > + u16 activation_dly; > u8 features; > }; > > @@ -806,7 +807,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi > *dsi, > if (ret < 0) > goto err_phy; > > - fsleep(1000); > + fsleep(dsi->info->activation_dly); > } > > return 0; > @@ -1534,6 +1535,7 @@ static const struct rzg2l_mipi_dsi_hw_info > rzg2l_mipi_dsi_info = { > DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | > DSIDPHYCTRL0_EN_BGR, > .min_dclk = 5803, > .max_dclk = 148500, > + .activation_dly = 1000, > }; > > static const struct of_device_id rzg2l_mipi_dsi_of_table[] = { > -- > 2.43.0 >
