On Wed, Apr 9, 2025 at 11:22 AM Konrad Dybcio
<konrad.dyb...@oss.qualcomm.com> wrote:
>
> On 4/9/25 5:12 PM, Connor Abbott wrote:
> > On Wed, Apr 9, 2025 at 10:48 AM Konrad Dybcio <konradyb...@kernel.org>
> > wrote:
> >>
> >> From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
> >>
> >> The Highest Bank address Bit value can change based on memory type used.
> >>
> >> Attempt to retrieve it dynamically, and fall back to a reasonable
> >> default (the one used prior to this change) on error.
> >>
> >> Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
> >> ---
> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 22 ++++++++++++++++------
> >> 1 file changed, 16 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> index
> >> 06465bc2d0b4b128cddfcfcaf1fe4252632b6777..0cc397378c99db35315209d0265ad9223e8b55c7
> >> 100644
> >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> @@ -13,6 +13,7 @@
> >> #include <linux/firmware/qcom/qcom_scm.h>
> >> #include <linux/pm_domain.h>
> >> #include <linux/soc/qcom/llcc-qcom.h>
> >> +#include <linux/soc/qcom/smem.h>
> >>
> >> #define GPU_PAS_ID 13
> >>
> >> @@ -669,17 +670,22 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu
> >> *gpu)
> >> static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> >> {
> >> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> >> + u32 hbb = qcom_smem_dram_get_hbb();
> >> + u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
> >> + u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle
> >> & 2);
> >> + u32 hbb_hi, hbb_lo;
> >> +
> >> /*
> >> * We subtract 13 from the highest bank bit (13 is the minimum
> >> value
> >> * allowed by hw) and write the lowest two bits of the remaining
> >> value
> >> * as hbb_lo and the one above it as hbb_hi to the hardware.
> >> */
> >> - BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
> >> - u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
> >> - u32 hbb_hi = hbb >> 2;
> >> - u32 hbb_lo = hbb & 3;
> >> - u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
> >> - u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle
> >> & 2);
> >> + if (hbb < 0)
> >> + hbb = adreno_gpu->ubwc_config.highest_bank_bit;
> >
> > No. The value we expose to userspace must match what we program.
> > You'll break VK_EXT_host_image_copy otherwise.
>
> I didn't know that was exposed to userspace.
>
> The value must be altered either way - ultimately, the hardware must
> receive the correct information. ubwc_config doesn't seem to be const,
> so I can edit it there if you like it better.
>
> Konrad
Yes, you should be calling qcom_smem_dram_get_hbb() in
a6xx_calc_ubwc_config(). You can already see there's a TODO there to
plug it in.
Connor
