[PATCH 3/4] drm/msm/a6xx: Get HBB dynamically, if available

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>

The Highest Bank address Bit value can change based on memory type used.

Attempt to retrieve it dynamically, and fall back to a reasonable
default (the one used prior to this change) on error.

Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 
06465bc2d0b4b128cddfcfcaf1fe4252632b6777..0cc397378c99db35315209d0265ad9223e8b55c7
 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -13,6 +13,7 @@
 #include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
+#include <linux/soc/qcom/smem.h>
 
 #define GPU_PAS_ID 13
 
@@ -669,17 +670,22 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
 {
        struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+       u32 hbb = qcom_smem_dram_get_hbb();
+       u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
+       u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);
+       u32 hbb_hi, hbb_lo;
+
        /*
         * We subtract 13 from the highest bank bit (13 is the minimum value
         * allowed by hw) and write the lowest two bits of the remaining value
         * as hbb_lo and the one above it as hbb_hi to the hardware.
         */
-       BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
-       u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
-       u32 hbb_hi = hbb >> 2;
-       u32 hbb_lo = hbb & 3;
-       u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
-       u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);
+       if (hbb < 0)
+               hbb = adreno_gpu->ubwc_config.highest_bank_bit;
+       hbb -= 13;
+       BUG_ON(hbb < 0);
+       hbb_hi = hbb >> 2;
+       hbb_lo = hbb & 3;
 
        gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
                  level2_swizzling_dis << 12 |
@@ -2467,6 +2473,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
        bool is_a7xx;
        int ret;
 
+       /* We need data from SMEM to retrieve HBB in set_ubwc_config() */
+       if (!qcom_smem_is_available())
+               return ERR_PTR(-EPROBE_DEFER);
+
        a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
        if (!a6xx_gpu)
                return ERR_PTR(-ENOMEM);

-- 
2.49.0