On Fri, 11 Apr 2025 at 12:49, Konrad Dybcio <konrad.dyb...@oss.qualcomm.com> wrote: > > On 4/9/25 5:49 PM, Konrad Dybcio wrote: > > On 4/9/25 5:44 PM, Dmitry Baryshkov wrote: > >> On 09/04/2025 17:47, Konrad Dybcio wrote: > >>> SMEM allows the OS to retrieve information about the DDR memory. > >>> Among that information, is a semi-magic value called 'HBB', or Highest > >>> Bank address Bit, which multimedia drivers (for hardware like Adreno > >>> and MDSS) must retrieve in order to program the IP blocks correctly. > >>> > >>> This series introduces an API to retrieve that value, uses it in the > >>> aforementioned programming sequences and exposes available DDR > >>> frequencies in debugfs (to e.g. pass to aoss_qmp debugfs). More > >>> information can be exposed in the future, as needed. > >> > >> I know that for some platforms HBB differs between GPU and DPU (as it's > >> being programmed currently). Is there a way to check, which values are we > >> going to program: > >> > >> - SM6115, SM6350, SM6375 (13 vs 14) > > SM6350 has INFO_V3 > SM6375 has INFO_V3_WITH_14_FREQS
I'm not completely sure what you mean here. I pointed out that these platforms disagreed upon the HBB value between the DPU/msm_mdss.c and a6xx_gpu.c. In some cases (a610/SM6115 and a619/SM6350) that was intentional to fix screen corruption issues. I don't remember if it was the case for QCM2290 or not. > > >> - SC8180X (15 vs 16) > > So I overlooked the fact that DDR info v3 (e.g. on 8180) doesn't provide > the HBB value.. Need to add some more sanity checks there. > > Maybe I can think up some fallback logic based on the DDR type reported. > > >> - QCM2290 (14 vs 15) > > I don't have one on hand, could you please give it a go on your RB1? > I would assume both it and SM6115 also provide v3 though.. > > Konrad -- With best wishes Dmitry
