Arbitrary symbol rate transmission by USRP2. I would like to transmit dqpsk 1,536,000sps with using benchmark_tx.py and benchmark_rx.py thru USRP2. Since USRP2 does have 100MHz as clock source. With the clock, seems decimation and interpolation only allow me at 1,538,461sps(100MHz/65) is the nearest.
I thought I need to make the clock which familiar to the desired symbol rate(1,536,000sps). Which I modify FPGA's DCM clock manager to prescale 100MHz by 3125 (100,000,000/3125=32KHz) and multiply it by 384(12.288Msps = 8x 1,536,000) and feed it to the DAC/ADC. I feel decimation and interpolation number is too huge for DCM. Would someone please advice me out where I should tackling to at first? Should I still go for modify DCM clock manager? Yoshiya Kato.
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