On 01/04/2010 07:29 AM, 加藤義也 wrote:
Arbitrary symbol rate transmission by USRP2.
I would like to transmit dqpsk 1,536,000sps with using benchmark_tx.py
and benchmark_rx.py thru USRP2.
Since USRP2 does have 100MHz as clock source.
With the clock, seems decimation and interpolation only allow me at
1,538,461sps(100MHz/65) is the nearest.
I thought I need to make the clock which familiar to the desired symbol
rate(1,536,000sps).
Which I modify FPGA's DCM clock manager to prescale 100MHz by 3125
(100,000,000/3125=32KHz) and
multiply it by 384(12.288Msps = 8x 1,536,000) and feed it to the DAC/ADC.
I feel decimation and interpolation number is too huge for DCM.
Would someone please advice me out where I should tackling to at first?
Should I still go for modify DCM clock manager?
Do not modify the DCM. That will not do what you want. What you will
need to do is make the software output samples at a rate which the USRP2
can handle. There are 2 ways to do that:
1 - Create a modulator which will output a non-integer number of samples
per symbol.
2 - Use the existing modulator, and add a rational resampler to your
transmit chain to get to a useful rate. The ratio between 1.536M and
100 M is 3125/48 or (5^5) / (2^4 * 3). So you would need to interpolate
by a total of 5^5 and decimate by 2^4*3. You can get 5^2 in the USRP2
interpolator by setting the main interpolator to 25. This means you
would be supplying 4 MS/s over the ethernet to the USRP2.
You would then generate you sample stream at 5 samples per symbol,
giving you 7.68 MS/s. Now the ratio between 7.68 MS/s and 4 MS/s is
only 25/48. So you would use the GNU Radio rational resampler block to
do this sample rate conversion, which is not hard.
Matt
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