On 2/25/07, Eric Blossom <[EMAIL PROTECTED]> wrote:
That sounds good. Would you interpret it as a delta-t from the timestamp in the header? I'm thinking about the case where there are multiple DELAY ops in the payload.
It would probably be best to interpret it as a delta from the current time tick where each operation would be 1 tick. If you did it as a delta from the timestamp header, you would have to calculate those intermediate deltas - and 32-bit subtractors inside an FPGA can run pretty slowly even with the fast carry chains. Something like: OP_WRITE_REG OP_DELAY[19] OP_I2C_WRITE I could see this showing OP_I2C_WRITE occuring 20 ticks after OP_WRITE_REG. What do you think?
Eric
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