From: Pankaj Bansal <pankaj.ban...@nxp.com>
LS1046A is QorIq Layerscape multicore communications processor with
four Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v2.
Co-authored-by: Vabhav Sharma <vabhav.sha...@nxp.com>
Co-authored-by: Pankaj Bansal <pankaj.ban...@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.ban...@nxp.com>
---
Silicon/NXP/LS1046A/LS1046A.dec | 13 ++++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 42 +++++++++++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 27 +++++++
Silicon/NXP/LS1046A/Include/Soc.h | 36 +++++++++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 78 ++++++++++++++++++++
5 files changed, 196 insertions(+)
diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index 000000000000..deb473b549c2
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,13 @@
+# LS1046A.dec
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001B
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
new file mode 100644
index 000000000000..dbe7f408fce9
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -0,0 +1,42 @@
+# LS1046A.dsc
+# LS1046A Soc package.
+#
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000
+
+[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+
+[PcdsFeatureFlag]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+##
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
new file mode 100644
index 000000000000..01ed0f6592d2
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+# @file
+#
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = ddd5f950-8816-4d38-8f98-f42b07333f78
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/LS1046A/LS1046A.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ChassisLib
+ DebugLib
+
+[Sources.common]
+ SocLib.c
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h
b/Silicon/NXP/LS1046A/Include/Soc.h
new file mode 100644
index 000000000000..6ff8db927865
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -0,0 +1,36 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include <Chassis.h>
+
+/**
+ Soc Memory Map
+**/
+#define LS1046A_DRAM0_PHYS_ADDRESS (BASE_2GB)
+#define LS1046A_DRAM0_SIZE (SIZE_2GB)
+#define LS1046A_DRAM1_PHYS_ADDRESS (BASE_32GB + BASE_2GB)
+#define LS1046A_DRAM1_SIZE (SIZE_32GB - SIZE_2GB) // 30 GB
+
+#define LS1046A_CCSR_PHYS_ADDRESS (BASE_16MB)
+#define LS1046A_CCSR_SIZE (SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LS1046A_QSPI0_PHYS_ADDRESS (BASE_1GB)
+#define LS1046A_QSPI0_SIZE (SIZE_512MB)
+
+#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+
+/**
+ Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
+
+#endif // SOC_H__
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
new file mode 100644
index 000000000000..3b15aee6ecae
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -0,0 +1,78 @@
+/** @Soc.c
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/ChassisLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SocLib.h>
+#include <Soc.h>
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multiplier/divider
+ values to be applied to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multiplier/divider values is
+ to be applied.
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP
clock
+ is to be retrieved.
+ @param[in] Args Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK,
then
+ the second argument will be interpreted as controller
+ number. e.g. if there are four i2c controllers in SOC,
+ then this value can be 0, 1, 2, 3
+ e.g. if ClockType is NXP_CORE_CLOCK, then second
+ argument is interpreted as cluster number and third
+ argument is interpreted as core number (within the
+ cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN NXP_IP_CLOCK ClockType,
+ IN VA_LIST Args
+ )
+{
+ LS1046A_DEVICE_CONFIG *Dcfg;
+ UINT32 RcwSr;
+ UINT64 ReturnValue;
+
+ ReturnValue = 0;
+ Dcfg = (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;
+
+ switch (ClockType) {
+ case NXP_UART_CLOCK:
+ case NXP_I2C_CLOCK:
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ ReturnValue >>= 1; // 1/2 Platform Clock
+ break;
+ default:
+ break;
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Function to initialize SoC specific constructs
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ ChassisInit ();
+
+ return;
+}
--
2.17.1
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