From: Pankaj Bansal <pankaj.ban...@nxp.com> for LS1043A SOC the DCFG registers are read in big endian format. However current Platofmr PLL calculation is being done assuing the little endian format.
Fix the Platform PLL calculation Signed-off-by: Pankaj Bansal <pankaj.ban...@nxp.com> --- Silicon/NXP/LS1043A/Include/Soc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h index 97a77d3f5da6..afcd9da34cda 100644 --- a/Silicon/NXP/LS1043A/Include/Soc.h +++ b/Silicon/NXP/LS1043A/Include/Soc.h @@ -48,7 +48,7 @@ /** Reset Control Word (RCW) Bits **/ -#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6 +#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6 typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG; -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#60578): https://edk2.groups.io/g/devel/message/60578 Mute This Topic: https://groups.io/mt/74627096/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
