On Fri, Jun 05, 2020 at 17:18:54 +0000, Pankaj Bansal (OSS) wrote: > > On Tue, Jun 02, 2020 at 18:54:59 +0530, Pankaj Bansal wrote: > > > From: Pankaj Bansal <pankaj.ban...@nxp.com> > > > > > > for LS1043A SOC the DCFG registers are read in big endian format. > > > However current Platofmr PLL calculation is being done assuing the > > > > Platform? assuming > > yes. typo mistake. > > > > > > little endian format. > > > > > > Fix the Platform PLL calculation > > > > OK, now I'm confused. > > DCFG is read using the DcfgRead32 function, which is supposed to > > handle the endianness issue. > > > > Ls1043a builds with > > gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE > > which means GetMmioOperations() returns the byte-swapping versions. > > > > Please clarify. > > OK. so this might be little confusing, so bear with me. > The reset configuration word (RCW) is 512 bits (1024 bits in LS2088 > / LS2160) long and contains all necessary configuration information > for the chip. RCW data is read from external memory (Nor flash or > SD/eMMC card or I2c eeprom) and written to the RCW status registers > (RCWSR) contained in the Device Configuration and Pin Control module > (DCSR), after which the device is configured as specified in the > RCW. > > The PreBoot Loader (PBL) fetches RCW data from the source memory > device and writes it to the RCW status registers. > Now the PBL fetches the data from flash in little endian format and > writes it to the DCSR registers in little endian format always. > This steps is same for all SOCs (LX2160 / LS1043 / LS1046 / LS2088).
This PBL is a ROM executing before the EDK2 code? > Now in SOCs where DCSR space is big endian (LS1043 / LS1046), we > read the RCWSR registers in big endian fashion. > This causes the bit position to be reversed. I'm still not following. We've set up this elaborate Rube Goldberg machine to be able to *not* have to carry separate header files for devices with individual components with registers that may be big- or little-endian depending on which SoC/version they are in. And now we have an implementation that states that its DcfgRead operations need to happan as big-endian. And the *only* time the Dcfg registers are accessed, we immediately need to change the header file to treat it as little-endian? What is the situation where Dcfg accesses *need* to be big-endian? Regards, Leif > In SOCs where DCSR space is little endian (LS2088 / LX2160), we read > the RCWSR registers in little endian fashion. > That is why the bit position is correct. > > > > > / > > Leif > > > > > Signed-off-by: Pankaj Bansal <pankaj.ban...@nxp.com> > > > --- > > > Silicon/NXP/LS1043A/Include/Soc.h | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h > > b/Silicon/NXP/LS1043A/Include/Soc.h > > > index 97a77d3f5da6..afcd9da34cda 100644 > > > --- a/Silicon/NXP/LS1043A/Include/Soc.h > > > +++ b/Silicon/NXP/LS1043A/Include/Soc.h > > > @@ -48,7 +48,7 @@ > > > /** > > > Reset Control Word (RCW) Bits > > > **/ > > > -#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6 > > > +#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6 > > > > > > typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG > > LS1043A_DEVICE_CONFIG; > > > > > > -- > > > 2.17.1 > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#60869): https://edk2.groups.io/g/devel/message/60869 Mute This Topic: https://groups.io/mt/74627096/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-