Hello,
The following NAND flash chips have been ordered today:
MT29F2G01ABAGDWB-IT:G
MT29F1G01ABAFDWB-IT:F
MT29F4G01ABAFDWB-IT:F
I have selected these references because, they are biiiig and
potentially useful, and the 2Gbit chip seems to have a different memory
layout.
I will not be able to write new code. Specifically if it's now AI reviewed.
But I will be able to run test code of your choosing on a raspi pico or
nucleo-l432kc
Sebastien
On 13/09/2024 22:43, Sebastien Lorquet wrote:
Hello,
Thank you for the additional information, of course I understand the
gsoc had to be completed in a limited time, and the current code is a
prototype.
I think it will be cool if we manage to make it production quality for
all users of the nuttx codebase.
I will probably send my farnell order next week so I'll have some
hardware to test with. the 4gbit micron chip is much larger than a nor
flash, and using it with a proper resilient fs will be nice.
If I get help with required software, we'll make it work.
On 9/13/24 22:09, Saurav Pal wrote:
Assuming the bytes are written to the flash from the start to
end (which I have not seen anything to suggest otherwise)
<terminator voice>Theoretically.</>
Joke apart, yes, it's a reasonable assumption. Sometimes it's word per
word not byte per byte, and even if the first bytes written could be
at the last address, I have never seen it done. However it is a good
design practice to explicitly separate the writing of the final CRC,
to make it obvious that you expect the previous write to be complete.
The design you described should work and inspires confidence.
Sebastien
