Hello,
Thank you for the additional information, of course I understand the
gsoc had to be completed in a limited time, and the current code is a
prototype.
I think it will be cool if we manage to make it production quality for
all users of the nuttx codebase.
I will probably send my farnell order next week so I'll have some
hardware to test with. the 4gbit micron chip is much larger than a nor
flash, and using it with a proper resilient fs will be nice.
If I get help with required software, we'll make it work.
On 9/13/24 22:09, Saurav Pal wrote:
Assuming the bytes are written to the flash from the start to
end (which I have not seen anything to suggest otherwise)
<terminator voice>Theoretically.</>
Joke apart, yes, it's a reasonable assumption. Sometimes it's word per
word not byte per byte, and even if the first bytes written could be at
the last address, I have never seen it done. However it is a good design
practice to explicitly separate the writing of the final CRC, to make it
obvious that you expect the previous write to be complete.
The design you described should work and inspires confidence.
Sebastien
