Expose the needed EEE register and defines.
Signed-off-by: Jeff Kirsher <jeffrey.t.kirs...@intel.com>
Signed-off-by: Guinan Sun <guinanx....@intel.com>
---
drivers/net/e1000/base/e1000_defines.h | 3 +++
drivers/net/e1000/base/e1000_i225.c | 12 +++---------
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/net/e1000/base/e1000_defines.h
b/drivers/net/e1000/base/e1000_defines.h
index 7f9c85451..86790c405 100644
--- a/drivers/net/e1000/base/e1000_defines.h
+++ b/drivers/net/e1000/base/e1000_defines.h
@@ -858,6 +858,7 @@
#define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
#define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */
#define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */
+#define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
#ifndef NO_I225_SUPPORT
#define E1000_EEE_LP_ADV_DEV_I225 7 /* EEE LP Adv Device */
#define E1000_EEE_LP_ADV_ADDR_I225 61 /* EEE LP Adv Register */
@@ -1056,6 +1057,8 @@
#define E1000_EECD_FLUPD_I225 0x00800000 /* Update FLASH */
#define E1000_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done
*/
#define E1000_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */
+#define E1000_FLUDONE_ATTEMPTS 20000
+#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
#endif /* NO_I225_SUPPORT */
#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
diff --git a/drivers/net/e1000/base/e1000_i225.c
b/drivers/net/e1000/base/e1000_i225.c
index 85c692644..5ace44546 100644
--- a/drivers/net/e1000/base/e1000_i225.c
+++ b/drivers/net/e1000/base/e1000_i225.c
@@ -406,8 +406,8 @@ STATIC s32 e1000_get_hw_semaphore_i225(struct e1000_hw *hw)
/* In rare circumstances, the SW semaphore may already be held
* unintentionally. Clear the semaphore once before giving up.
*/
- if (hw->dev_spec._82575.clear_semaphore_once) {
- hw->dev_spec._82575.clear_semaphore_once = false;
+ if (hw->dev_spec._i225.clear_semaphore_once) {
+ hw->dev_spec._i225.clear_semaphore_once = false;
e1000_put_hw_semaphore_generic(hw);
for (i = 0; i < timeout; i++) {
swsm = E1000_READ_REG(hw, E1000_SWSM);
@@ -1147,7 +1147,7 @@ s32 e1000_set_eee_i225(struct e1000_hw *hw, bool adv2p5G,
bool adv1G,
eeer = E1000_READ_REG(hw, E1000_EEER);
/* enable or disable per user setting */
- if (!(hw->dev_spec._82575.eee_disable)) {
+ if (!(hw->dev_spec._i225.eee_disable)) {
u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
if (adv100M)
@@ -1168,12 +1168,6 @@ s32 e1000_set_eee_i225(struct e1000_hw *hw, bool
adv2p5G, bool adv1G,
eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
E1000_EEER_LPI_FC);
-#ifndef EXTERNAL_RELEASE
- /*
- * This bit is supposed to be cleared by the NVM. However, older
- * NVMs may not have done this (Springville HW HSD #359296).
- */
-#endif /* EXTERNAL_RELEASE */
/* This bit should not be set in normal operation. */
if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
--
2.17.1
