Legacy PTP support for i225 device required time synchronization
registers. This patch add wrap to expose these registers to igc core
files.
Signed-off-by: Sasha Neftin <sasha.nef...@intel.com>
Signed-off-by: Guinan Sun <guinanx....@intel.com>
---
drivers/net/e1000/base/e1000_82575.h | 8 ---
drivers/net/e1000/base/e1000_defines.h | 69 ++++++++++++++++++++++++++
drivers/net/e1000/base/e1000_regs.h | 10 ++++
3 files changed, 79 insertions(+), 8 deletions(-)
diff --git a/drivers/net/e1000/base/e1000_82575.h
b/drivers/net/e1000/base/e1000_82575.h
index fb810a4b3..d8ea3ae1f 100644
--- a/drivers/net/e1000/base/e1000_82575.h
+++ b/drivers/net/e1000/base/e1000_82575.h
@@ -148,14 +148,12 @@ struct e1000_adv_context_desc {
/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
#define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
#define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
-#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
#define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
#define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
#define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
#define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
#define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
#define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
-#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
#define E1000_RXDADV_RSSTYPE_MASK 0x0000000F
#define E1000_RXDADV_RSSTYPE_SHIFT 12
@@ -164,7 +162,6 @@ struct e1000_adv_context_desc {
#define E1000_RXDADV_SPLITHEADER_EN 0x00001000
#define E1000_RXDADV_SPH 0x8000
#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
-#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
#define E1000_RXDADV_ERR_HBO 0x00800000
/* RSS Hash results */
@@ -251,7 +248,6 @@ struct e1000_adv_context_desc {
/* ETQF register bit definitions */
#define E1000_ETQF_FILTER_ENABLE (1 << 26)
#define E1000_ETQF_IMM_INT (1 << 29)
-#define E1000_ETQF_1588 (1 << 30)
/*
* ETQF filter list: one static filter per filter consumer. This is
@@ -263,10 +259,6 @@ struct e1000_adv_context_desc {
*/
#define E1000_ETQF_FILTER_EAPOL 0
-#define E1000_FTQF_VF_BP 0x00008000
-#define E1000_FTQF_1588_TIME_STAMP 0x08000000
-#define E1000_FTQF_MASK 0xF0000000
-#define E1000_FTQF_MASK_PROTO_BP 0x10000000
#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
#define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000
#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
diff --git a/drivers/net/e1000/base/e1000_defines.h
b/drivers/net/e1000/base/e1000_defines.h
index 86790c405..b132d5ee2 100644
--- a/drivers/net/e1000/base/e1000_defines.h
+++ b/drivers/net/e1000/base/e1000_defines.h
@@ -784,6 +784,75 @@
#define E1000_TIMINCA_INCPERIOD_SHIFT 24
#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
+/* Time Sync Interrupt Cause/Mask Register Bits */
+#define TSINTR_SYS_WRAP (1 << 0) /* SYSTIM Wrap around. */
+#define TSINTR_TXTS (1 << 1) /* Transmit Timestamp. */
+#define TSINTR_TT0 (1 << 3) /* Target Time 0 Trigger. */
+#define TSINTR_TT1 (1 << 4) /* Target Time 1 Trigger. */
+#define TSINTR_AUTT0 (1 << 5) /* Auxiliary Timestamp 0 Taken. */
+#define TSINTR_AUTT1 (1 << 6) /* Auxiliary Timestamp 1 Taken. */
+
+#define TSYNC_INTERRUPTS TSINTR_TXTS
+
+/* TSAUXC Configuration Bits */
+#define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */
+#define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */
+#define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */
+#define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */
+#define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */
+#define TSAUXC_ST1 (1 << 7) /* Start Clock 1 Toggle on Target Time 1. */
+#define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */
+#define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */
+
+/* SDP Configuration Bits */
+#define AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */
+#define AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */
+#define AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */
+#define AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */
+#define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
+#define AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */
+#define AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */
+#define AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */
+#define AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */
+#define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */
+#define TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */
+#define TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */
+#define TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */
+#define TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */
+#define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0.
*/
+#define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0.
*/
+#define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1.
*/
+#define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1.
*/
+#define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0.
*/
+#define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0.
*/
+#define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1.
*/
+#define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1.
*/
+#define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2.
*/
+#define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2.
*/
+#define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2.
*/
+#define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2.
*/
+#define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3.
*/
+#define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3.
*/
+#define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3.
*/
+#define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3.
*/
+
+#define E1000_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */
+#define E1000_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */
+
+/* Extended Device Control */
+#define E1000_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */
+
+/* ETQF register bit definitions */
+#define E1000_ETQF_1588 (1 << 30)
+#define E1000_FTQF_VF_BP 0x00008000
+#define E1000_FTQF_1588_TIME_STAMP 0x08000000
+#define E1000_FTQF_MASK 0xF0000000
+#define E1000_FTQF_MASK_PROTO_BP 0x10000000
+/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
+#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
+#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
+
+#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
#define E1000_TSICR_TXTS 0x00000002
#define E1000_TSIM_TXTS 0x00000002
/* TUPLE Filtering Configuration */
diff --git a/drivers/net/e1000/base/e1000_regs.h
b/drivers/net/e1000/base/e1000_regs.h
index 7a6cb7ce9..2e14ce109 100644
--- a/drivers/net/e1000/base/e1000_regs.h
+++ b/drivers/net/e1000/base/e1000_regs.h
@@ -698,4 +698,14 @@
+/* IEEE 1588 TIMESYNCH */
+#define E1000_TRGTTIML0 0x0B644 /* Target Time Register 0 Low - RW */
+#define E1000_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */
+#define E1000_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */
+#define E1000_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */
+#define E1000_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */
+#define E1000_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */
+#define E1000_TSSDP 0x0003C /* Time Sync SDP Configuration Register - RW */
+
+
#endif
--
2.17.1
