configure.ac | 69
src/AtomBios/CD_Operations.c | 954 +++++++
src/AtomBios/Decoder.c | 235 +
src/AtomBios/hwserv_drv.c | 348 ++
src/AtomBios/includes/CD_Common_Types.h | 154 +
src/AtomBios/includes/CD_Definitions.h | 49
src/AtomBios/includes/CD_Opcodes.h | 181 +
src/AtomBios/includes/CD_Structs.h | 464 +++
src/AtomBios/includes/CD_binding.h | 46
src/AtomBios/includes/CD_hw_services.h | 318 ++
src/AtomBios/includes/Decoder.h | 86
src/AtomBios/includes/ObjectID.h | 448 +++
src/AtomBios/includes/atombios.h | 4306 ++++++++++++++++++++++++++++++++
src/AtomBios/includes/regsdef.h | 25
src/Makefile.am | 48
src/ati_pciids_gen.h | 132
src/atipciids.h | 7
src/atombios_crtc.c | 381 ++
src/atombios_output.c | 613 ++++
src/pcidb/ati_pciids.csv | 132
src/radeon.h | 220 -
src/radeon_accel.c | 9
src/radeon_accelfuncs.c | 2
src/radeon_atombios.c | 2625 +++++++++++++++++++
src/radeon_atombios.h | 235 +
src/radeon_atomwrapper.c | 101
src/radeon_atomwrapper.h | 31
src/radeon_bios.c | 329 +-
src/radeon_chipinfo_gen.h | 132
src/radeon_chipset_gen.h | 132
src/radeon_crtc.c | 254 +
src/radeon_cursor.c | 144 -
src/radeon_display.c | 15
src/radeon_dri.c | 4
src/radeon_driver.c | 1365 ++++++++--
src/radeon_exa_funcs.c | 8
src/radeon_macros.h | 53
src/radeon_modes.c | 16
src/radeon_output.c | 979 ++++---
src/radeon_pci_chipset_gen.h | 132
src/radeon_probe.c | 2
src/radeon_probe.h | 361 ++
src/radeon_reg.h | 461 +++
src/radeon_render.c | 4
src/radeon_tv.c | 4
src/radeon_tv.h | 5
src/radeon_video.c | 84
47 files changed, 15525 insertions(+), 1178 deletions(-)
New commits:
commit be7f8fd338f5af8b632f16a83db41e15d00af469
Author: Dave Airlie <[EMAIL PROTECTED]>
Date: Fri Dec 21 10:03:49 2007 +1000
fix mode bandwidth configure check
diff --git a/configure.ac b/configure.ac
index 159eced..edac3ed 100644
--- a/configure.ac
+++ b/configure.ac
@@ -216,7 +216,8 @@ AC_CHECK_DECL(xf86XVFillKeyHelperDrawable,
AC_CHECK_DECL(xf86ModeBandwidth,
[AC_DEFINE(HAVE_XF86MODEBANDWIDTH, 1, [Have xf86ModeBandwidth
prototype])],
[],
- [#include "xf86Modes.h"])
+ [#include "xorg-server.h"
+ #include "xf86Modes.h"])
AC_CHECK_DECL(xf86_crtc_clip_video_helper,
[AC_DEFINE(HAVE_XF86CRTCCLIPVIDEOHELPER, 1, [Have
xf86_crtc_clip_video_helper prototype])],
commit 3f9b597dedc45379b0bc0b631f3f924c403bca48
Author: Dave Airlie <[EMAIL PROTECTED]>
Date: Fri Dec 21 09:55:42 2007 +1000
fixup clip test include handling
diff --git a/configure.ac b/configure.ac
index 91ea4a8..159eced 100644
--- a/configure.ac
+++ b/configure.ac
@@ -221,7 +221,10 @@ AC_CHECK_DECL(xf86ModeBandwidth,
AC_CHECK_DECL(xf86_crtc_clip_video_helper,
[AC_DEFINE(HAVE_XF86CRTCCLIPVIDEOHELPER, 1, [Have
xf86_crtc_clip_video_helper prototype])],
[],
- [#include "xf86Crtc.h"])
+ [#include <X11/Xmd.h>
+ #include "xorg-server.h"
+ #include "xf86i2c.h"
+ #include "xf86Crtc.h"])
AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
[XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
commit 9a5b501332c0a1f10af20845af48c9ddd2ce26a0
Author: Dave Airlie <[EMAIL PROTECTED]>
Date: Fri Dec 21 09:45:55 2007 +1000
set ddc line correctly post-merge
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index b4a69a3..752b31e 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -421,7 +421,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS
(ScrnInfoPtr pScrn)
info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
info->BiosConnector[0].DACType = DAC_PRIMARY;
info->BiosConnector[0].TMDSType = TMDS_INT;
- info->BiosConnector[0].DDCType = DDC_DVI;
+ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC;
} else
return FALSE;
}
commit eb99c3c5c9a2249cb84920f0f225e525fc3a4144
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Thu Dec 20 18:14:38 2007 -0500
Bump for RC release
diff --git a/configure.ac b/configure.ac
index ae5cb2b..48302d2 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.7.196,
+ 6.7.197,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
commit 8d49ff1da917b7f8240267953ef6ce4ff04daecb
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Thu Dec 20 01:09:57 2007 -0500
RADEON: check for xf86_crtc_clip_video_helper() in configure.ac
use xf86_crtc_clip_video_helper() from the server if available.
diff --git a/configure.ac b/configure.ac
index cc4d490..ae5cb2b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -209,6 +209,11 @@ AC_CHECK_DECL(xf86ModeBandwidth,
[],
[#include "xf86Modes.h"])
+AC_CHECK_DECL(xf86_crtc_clip_video_helper,
+ [AC_DEFINE(HAVE_XF86CRTCCLIPVIDEOHELPER, 1, [Have
xf86_crtc_clip_video_helper prototype])],
+ [],
+ [#include "xf86Crtc.h"])
+
AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
[XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
[#include "xorg-server.h"])
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 3f0209e..2b5764f 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -119,6 +119,7 @@ static Atom xvOvAlpha, xvGrAlpha, xvAlphaMode;
#define GET_PORT_PRIVATE(pScrn) \
(RADEONPortPrivPtr)((RADEONPTR(pScrn))->adaptor->pPortPrivates[0].ptr)
+#ifndef HAVE_XF86CRTCCLIPVIDEOHELPER
static void
radeon_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b)
{
@@ -185,17 +186,17 @@ radeon_covering_crtc(ScrnInfoPtr pScrn,
}
static Bool
-radeon_clip_video_helper(ScrnInfoPtr pScrn,
- xf86CrtcPtr *crtc_ret,
- xf86CrtcPtr desired_crtc,
- BoxPtr dst,
- INT32 *xa,
- INT32 *xb,
- INT32 *ya,
- INT32 *yb,
- RegionPtr reg,
- INT32 width,
- INT32 height)
+radeon_crtc_clip_video_helper(ScrnInfoPtr pScrn,
+ xf86CrtcPtr *crtc_ret,
+ xf86CrtcPtr desired_crtc,
+ BoxPtr dst,
+ INT32 *xa,
+ INT32 *xb,
+ INT32 *ya,
+ INT32 *yb,
+ RegionPtr reg,
+ INT32 width,
+ INT32 height)
{
Bool ret;
RegionRec crtc_region_local;
@@ -227,6 +228,31 @@ radeon_clip_video_helper(ScrnInfoPtr pScrn,
return ret;
}
+#endif
+
+static Bool
+radeon_crtc_clip_video(ScrnInfoPtr pScrn,
+ xf86CrtcPtr *crtc_ret,
+ xf86CrtcPtr desired_crtc,
+ BoxPtr dst,
+ INT32 *xa,
+ INT32 *xb,
+ INT32 *ya,
+ INT32 *yb,
+ RegionPtr reg,
+ INT32 width,
+ INT32 height)
+{
+#ifndef HAVE_XF86CRTCCLIPVIDEOHELPER
+ return radeon_crtc_clip_video_helper(pScrn, crtc_ret, desired_crtc,
+ dst, xa, xb, ya, yb,
+ reg, width, height);
+#else
+ return xf86_crtc_clip_video_helper(pScrn, crtc_ret, desired_crtc,
+ dst, xa, xb, ya, yb,
+ reg, width, height);
+#endif
+}
#ifdef USE_EXA
static void
@@ -2899,9 +2925,9 @@ RADEONPutImage(
dstBox.y1 = drw_y;
dstBox.y2 = drw_y + drw_h;
- if (!radeon_clip_video_helper(pScrn, &crtc, pPriv->desired_crtc,
- &dstBox, &xa, &xb, &ya, &yb,
- clipBoxes, width, height))
+ if (!radeon_crtc_clip_video(pScrn, &crtc, pPriv->desired_crtc,
+ &dstBox, &xa, &xb, &ya, &yb,
+ clipBoxes, width, height))
return Success;
if (!crtc) {
@@ -3295,9 +3321,9 @@ RADEONDisplaySurface(
dstBox.y1 = drw_y;
dstBox.y2 = drw_y + drw_h;
- if (!radeon_clip_video_helper(pScrn, &crtc, portPriv->desired_crtc,
- &dstBox, &xa, &xb, &ya, &yb, clipBoxes,
- surface->width, surface->height))
+ if (!radeon_crtc_clip_video(pScrn, &crtc, portPriv->desired_crtc,
+ &dstBox, &xa, &xb, &ya, &yb, clipBoxes,
+ surface->width, surface->height))
return Success;
if (!crtc) {
@@ -3438,9 +3464,9 @@ RADEONPutVideo(
else
vbi_line_width = 2000; /* might need adjustment */
- if (!radeon_clip_video_helper(pScrn, &crtc, pPriv->desired_crtc,
- &dstBox, &xa, &xb, &ya, &yb,
- clipBoxes, width, height))
+ if (!radeon_crtc_clip_video(pScrn, &crtc, pPriv->desired_crtc,
+ &dstBox, &xa, &xb, &ya, &yb,
+ clipBoxes, width, height))
return Success;
if (!crtc) {
commit fb7a4e24f2da3561ef81371ca4013a4f13806e91
Author: Adam Jackson <[EMAIL PROTECTED]>
Date: Wed Dec 19 19:15:19 2007 -0500
Fix RN50 mode filtering.
The old code would attempt to limit the maximum pixel size of the screen
by limiting the maximum PLL frequency. This ends up confusing the PLL
computation code since sometimes your maximum freq can be lower than your
minimum freq. More to the point it's just wrong, maximum PLL frequency
isn't the same thing as maximum pixel clock, and even that isn't the same
thing as maximum scanout pixels per second.
The correct thing to do is filter by the mode's effective memory bandwidth.
diff --git a/configure.ac b/configure.ac
index 1570e54..cc4d490 100644
--- a/configure.ac
+++ b/configure.ac
@@ -204,6 +204,11 @@ AC_CHECK_DECL(xf86XVFillKeyHelperDrawable,
[],
[#include <xf86xv.h>])
+AC_CHECK_DECL(xf86ModeBandwidth,
+ [AC_DEFINE(HAVE_XF86MODEBANDWIDTH, 1, [Have xf86ModeBandwidth
prototype])],
+ [],
+ [#include "xf86Modes.h"])
+
AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
[XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
[#include "xorg-server.h"])
diff --git a/src/radeon.h b/src/radeon.h
index 03db360..801d616 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -41,6 +41,7 @@
#include <unistd.h> /* For usleep() */
#include <sys/time.h> /* For gettimeofday() */
+#include "config.h"
#include "xf86str.h"
#include "compiler.h"
#include "xf86fbman.h"
@@ -97,6 +98,11 @@
#define MIN(a,b) ((a)>(b)?(b):(a))
#endif
+#ifndef HAVE_XF86MODEBANDWIDTH
+extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth);
+#define MODE_BANDWIDTH MODE_BAD
+#endif
+
typedef enum {
OPTION_NOACCEL,
OPTION_SW_CURSOR,
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 25b2119..9f9fd90 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1051,18 +1051,6 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
info->mclk = 200.00;
}
- if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
- /* Avoid RN50 corruption due to memory bandwidth starvation.
- * 18 is an empirical value based on the databook and Windows driver.
- *
- * Empirical value changed to 24 to raise pixel clock limit and
- * allow higher resolution modes on capable monitors
- */
- pll->max_pll_freq = min(pll->max_pll_freq,
- 24 * info->mclk * 100 / pScrn->bitsPerPixel *
- info->RamWidth / 16);
- }
-
/* card limits for computing PLLs */
pll->min_ref_div = 2;
pll->max_ref_div = 0x3ff;
@@ -5380,10 +5368,44 @@ Bool RADEONHandleMessage(int scrnIndex, const char*
msgtype,
}
#endif
+#ifndef HAVE_XF86MODEBANDWIDTH
+/** Calculates the memory bandwidth (in MiB/sec) of a mode. */
+_X_HIDDEN unsigned int
+xf86ModeBandwidth(DisplayModePtr mode, int depth)
+{
+ float a_active, a_total, active_percent, pixels_per_second;
+ int bytes_per_pixel = (depth + 7) / 8;
+
+ if (!mode->HTotal || !mode->VTotal || !mode->Clock)
+ return 0;
+
+ a_active = mode->HDisplay * mode->VDisplay;
+ a_total = mode->HTotal * mode->VTotal;
+ active_percent = a_active / a_total;
+ pixels_per_second = active_percent * mode->Clock * 1000.0;
+
+ return (unsigned int)(pixels_per_second * bytes_per_pixel / (1024 * 1024));
+}
+#endif
+
/* Used to disallow modes that are not supported by the hardware */
ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode,
Bool verbose, int flag)
{
+ ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+
+ /*
+ * RN50 has effective maximum mode bandwidth of about 300MiB/s.
+ * XXX should really do this for all chips by properly computing
+ * memory bandwidth and an overhead factor.
+ */
+ if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
+ if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300)
+ return MODE_BANDWIDTH;
+ }
+
/* There are problems with double scan mode at high clocks
* They're likely related PLL and display buffer settings.
* Disable these modes for now.
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 9850702..64c0438 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -789,6 +789,19 @@ static int
radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ ScrnInfoPtr pScrn = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+
+ /*
+ * RN50 has effective maximum mode bandwidth of about 300MiB/s.
+ * XXX should really do this for all chips by properly computing
+ * memory bandwidth and an overhead factor.
+ */
+ if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
+ if (xf86ModeBandwidth(pMode, pScrn->bitsPerPixel) > 300)
+ return MODE_BANDWIDTH;
+ }
if (radeon_output->type == OUTPUT_STV ||
radeon_output->type == OUTPUT_CTV) {
commit 0e6634870d1ab38ee8c83f6bda1ba60364997853
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Wed Dec 19 11:54:27 2007 -0500
RADEON: skip empty connectors when creating outputs
diff --git a/src/radeon_output.c b/src/radeon_output.c
index c60ece8..115666d 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -3217,6 +3217,10 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
+
+ if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE)
+ continue;
+
RADEONOutputPrivatePtr radeon_output =
xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
if (!radeon_output) {
return FALSE;
commit 6afbf718c151dc3c5c59bd3136b58a93a114d798
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Wed Dec 19 11:48:38 2007 -0500
RADEON: add support for legacy radeons with DVI and no connector table
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index d150c4b..7d4d12a 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -277,7 +277,21 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS
(ScrnInfoPtr pScrn)
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table
found!\n");
- return FALSE;
+
+ /* old radeons and r128 didn't use connector tables you just check
+ * for LVDS, DVI, TV, etc. tables
+ */
+ offset = RADEON_BIOS16(info->ROMHeaderStart + 0x34);
+ if (offset) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Found DFP table, assuming DVI connector\n");
+ info->BiosConnector[0].valid = TRUE;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
+ info->BiosConnector[0].DACType = DAC_PRIMARY;
+ info->BiosConnector[0].TMDSType = TMDS_INT;
+ info->BiosConnector[0].DDCType = DDC_DVI;
+ } else
+ return FALSE;
}
/* check LVDS table */
commit f5e8c185001e62e744310667c2d1bd3fe6542a62
Author: Dave Airlie <[EMAIL PROTECTED]>
Date: Wed Dec 19 10:38:58 2007 +1000
more endian related fixage
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 2b7f0e8..278d5a7 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -251,7 +251,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int
y, int w, int h,
#endif
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- unsigned int swapper = info->ModeReg.surface_cntl &
+ unsigned int swapper = info->ModeReg->surface_cntl &
~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP |
RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP);
#endif
@@ -311,7 +311,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int
y, int w, int h,
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
return TRUE;
@@ -354,7 +354,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x,
int y, int w, int h,
RINFO_FROM_SCREEN(pSrc->drawable.pScreen);
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- unsigned int swapper = info->ModeReg.surface_cntl &
+ unsigned int swapper = info->ModeReg->surface_cntl &
~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP |
RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP);
#endif
@@ -492,7 +492,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x,
int y, int w, int h,
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
return TRUE;
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 99b74eb..a84662e 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -2156,7 +2156,7 @@ RADEONCopyData(
{
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- unsigned int swapper = info->ModeReg.surface_cntl &
+ unsigned int swapper = info->ModeReg->surface_cntl &
~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP |
RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP);
@@ -2182,7 +2182,7 @@ RADEONCopyData(
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
}
}
@@ -2238,7 +2238,7 @@ RADEONCopyRGB24Data(
{
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl
+ OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl
| RADEON_NONSURF_AP0_SWP_32BPP)
& ~RADEON_NONSURF_AP0_SWP_16BPP);
#endif
@@ -2254,7 +2254,7 @@ RADEONCopyRGB24Data(
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
}
}
@@ -2333,7 +2333,7 @@ RADEONCopyMungedData(
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl
+ OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl
| RADEON_NONSURF_AP0_SWP_32BPP)
& ~RADEON_NONSURF_AP0_SWP_16BPP);
#endif
@@ -2371,7 +2371,7 @@ RADEONCopyMungedData(
}
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
}
}
commit 98b247066d00db66abe91f518cd93b5c4da4cfb4
Author: Dave Airlie <[EMAIL PROTECTED]>
Date: Wed Dec 19 10:25:41 2007 +1000
fix big endian build since zaphod fixups
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 6133b2c..5b04848 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -74,12 +74,12 @@
#define CURSOR_SWAPPING_START() \
do { \
OUTREG(RADEON_SURFACE_CNTL, \
- (info->ModeReg.surface_cntl | \
+ (info->ModeReg->surface_cntl | \
RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \
~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP)); \
} while (0)
#define CURSOR_SWAPPING_END() (OUTREG(RADEON_SURFACE_CNTL, \
- info->ModeReg.surface_cntl))
+ info->ModeReg->surface_cntl))
#else
diff --git a/src/radeon_render.c b/src/radeon_render.c
index 490dec1..a80d136 100644
--- a/src/radeon_render.c
+++ b/src/radeon_render.c
@@ -317,7 +317,7 @@ static Bool RADEONSetupRenderByteswap(ScrnInfoPtr pScrn,
int tex_bytepp)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- CARD32 swapper = info->ModeReg.surface_cntl;
+ CARD32 swapper = info->ModeReg->surface_cntl;
swapper &= ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP |
RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP);
@@ -345,7 +345,7 @@ static void RADEONRestoreByteswap(RADEONInfoPtr info)
{
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
}
#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */
commit bd7206fa120495037e3fea0c920d0031d7715bf6
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Tue Dec 18 03:03:11 2007 -0500
RADEON: fix another merge error
this broken legacy radeons
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index eb892f2..2d4ac15 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -953,7 +953,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll,
adjusted_mode, pll_flags);
+ RADEONInitPLLRegisters(pScrn, info->ModeReg, &info->pll,
adjusted_mode, pll_flags);
} else {
info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div;
info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3;
@@ -967,7 +967,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll2\n");
- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll,
adjusted_mode, pll_flags);
+ RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll,
adjusted_mode, pll_flags);
}
break;
}
commit 65a3ac7530e11bb7d818a988fd0cf1dde7688fa4
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Tue Dec 18 00:15:38 2007 -0500
RADEON: more PLL tweaks
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index ea12556..eb892f2 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -620,7 +620,7 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr
save,
}
-static int RADEONDiv(int n, int d)
+static CARD32 RADEONDiv(CARD64 n, CARD32 d)
{
return (n + (d / 2)) / d;
}
@@ -645,7 +645,7 @@ RADEONComputePLL(RADEONPLLPtr pll,
CARD32 best_vco_diff = 1;
CARD32 post_div;
- freq = freq / 10;
+ freq = freq * 1000;
ErrorF("freq: %lu\n", freq);
@@ -654,7 +654,7 @@ RADEONComputePLL(RADEONPLLPtr pll,
for (post_div = pll->min_post_div; post_div <= pll->max_post_div;
++post_div) {
CARD32 ref_div;
- CARD32 vco = freq * post_div;
+ CARD32 vco = (freq / 10000) * post_div;
if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
continue;
@@ -679,21 +679,22 @@ RADEONComputePLL(RADEONPLLPtr pll,
if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
continue;
- feedback_div = RADEONDiv(freq * ref_div * post_div,
- pll->reference_freq);
+ feedback_div = RADEONDiv((CARD64)freq * ref_div * post_div,
+ pll->reference_freq * 10000);
if (feedback_div < pll->min_feedback_div || feedback_div >
pll->max_feedback_div)
continue;
- current_freq = RADEONDiv(pll->reference_freq * feedback_div,
+ current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 *
feedback_div,
ref_div * post_div);
error = abs(current_freq - freq);
vco_diff = abs(vco - best_vco);
if ((best_vco == 0 && error < best_error) ||
+ (ref_div == pll->reference_div) ||
(best_vco != 0 &&
- (error < best_error - 1000 ||
+ (error < best_error - 100 ||
(abs(error - best_error) < 100 && vco_diff < best_vco_diff
)))) {
best_post_div = post_div;
best_ref_div = ref_div;
@@ -710,7 +711,7 @@ RADEONComputePLL(RADEONPLLPtr pll,
ErrorF("best_ref_div: %u\n", best_ref_div);
ErrorF("best_post_div: %u\n", best_post_div);
- *chosen_dot_clock_freq = best_freq;
+ *chosen_dot_clock_freq = best_freq / 10000;
*chosen_feedback_div = best_feedback_div;
*chosen_reference_div = best_ref_div;
*chosen_post_div = best_post_div;
commit d93a0e10b8bc6e3797a3cf6c1e28ca413a7c38e4
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Mon Dec 17 20:32:45 2007 -0500
RADEON: post div tweaks for legacy radeon
diff --git a/src/radeon.h b/src/radeon.h
index a5717a0..7d57ca5 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -203,6 +203,7 @@ typedef struct {
#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
#define RADEON_PLL_USE_REF_DIV (1 << 2)
+#define RADEON_PLL_LEGACY (1 << 3)
typedef struct {
CARD16 reference_freq;
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 5e9db39..ea12556 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -659,6 +659,16 @@ RADEONComputePLL(RADEONPLLPtr pll,
if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
continue;
+ /* legacy radeons only have a few post_divs */
+ if (flags & RADEON_PLL_LEGACY) {
+ if ((post_div == 5) ||
+ (post_div == 7) ||
+ (post_div == 9) ||
+ (post_div == 10) ||
+ (post_div == 11))
+ continue;
+ }
+
if (vco < pll->pll_out_min || vco > pll->pll_out_max)
continue;
@@ -893,7 +903,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
Bool tilingOld = info->tilingEnabled;
int i = 0;
double dot_clock = 0;
- int pll_flags = 0;
+ int pll_flags = RADEON_PLL_LEGACY;
Bool update_tv_routing = FALSE;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 3eecedb..2002dd3 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1239,7 +1239,7 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
pll->min_post_div = 2;
pll->max_post_div = 0x7f;
} else {
- pll->min_post_div = 2;
+ pll->min_post_div = 1;
pll->max_post_div = 12; //16 on crtc0
}
pll->min_ref_div = 2;
commit 03b8b49f6f502c45552b018fd8c44d366b2d576f
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Mon Dec 17 20:20:04 2007 -0500
RADEON: fix typo from merge
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index d2271b0..5e9db39 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -625,7 +625,7 @@ static int RADEONDiv(int n, int d)
return (n + (d / 2)) / d;
}
-static void
+void
RADEONComputePLL(RADEONPLLPtr pll,
unsigned long freq,
CARD32 *chosen_dot_clock_freq,
commit 29706ca585ebd9b7b3521521a17016322e9ecccb
Author: Dave Airlie <[EMAIL PROTECTED]>
Date: Tue Dec 18 10:55:38 2007 +1000
fixup shadow setup on !r600
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 62e7cd0..3d2c802 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -3939,8 +3939,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
RADEONInitVideo(pScreen);
}
- if (!shadowSetup(pScreen)) {
- return FALSE;
+ if (info->r600_shadow_fb == TRUE) {
+ if (!shadowSetup(pScreen)) {
+ return FALSE;
+ }
}
/* Provide SaveScreen & wrap BlockHandler and CloseScreen */
commit 2a134af01bc85de758ad83a85b23d1bba4a1a0f5
Author: Dave Airlie <[EMAIL PROTECTED]>
Date: Mon Dec 17 15:00:36 2007 +1000
r600: add shadow support to r600 driver to at least make 2d useable
diff --git a/src/radeon.h b/src/radeon.h
index 6c38826..6cc2b6f 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -710,6 +710,9 @@ typedef struct {
Bool IsSecondary;
Bool IsPrimary;
+
+ Bool r600_shadow_fb;
+ void *fb_shadow;
} RADEONInfoRec, *RADEONInfoPtr;
#define RADEONWaitForFifo(pScrn, entries) \
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index ac307ab..62e7cd0 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -97,6 +97,7 @@
#include "xf86cmap.h"
#include "vbe.h"
+#include "shadow.h"
/* vgaHW definitions */
#ifdef WITH_VGAHW
#include "vgaHW.h"
@@ -347,6 +348,15 @@ static const char *i2cSymbols[] = {
NULL
};
+static const char *shadowSymbols[] = {
+ "shadowAdd",
+ "shadowInit",
+ "shadowSetup",
+ "shadowUpdatePacked",
+ "shadowUpdatePackedWeak",
+ NULL
+};
+
void RADEONLoaderRefSymLists(void)
{
/*
@@ -405,23 +415,41 @@ struct RADEONInt10Save {
static Bool RADEONMapMMIO(ScrnInfoPtr pScrn);
static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn);
-#if 0
+static void *
+radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
+ CARD32 *size, void *closure)
+{
+ ScrnInfoPtr pScrn = xf86Screens[screen->myNum];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ int stride;
+
+ stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
+ *size = stride;
+
+ return ((CARD8 *)info->FB + pScrn->fbOffset +
+ row * stride + offset);
+}
static Bool
RADEONCreateScreenResources (ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
+ PixmapPtr pixmap;
pScreen->CreateScreenResources = info->CreateScreenResources;
if (!(*pScreen->CreateScreenResources)(pScreen))
return FALSE;
+ pScreen->CreateScreenResources = RADEONCreateScreenResources;
- if (!xf86RandR12CreateScreenResources(pScreen))
- return FALSE;
+ if (info->r600_shadow_fb) {
+ pixmap = pScreen->GetScreenPixmap(pScreen);
- return TRUE;
+ if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(),
+ radeonShadowWindow, 0, NULL))
+ return FALSE;
+ }
+ return TRUE;
}
-#endif
RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn)
{
@@ -1930,6 +1958,14 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
info->Chipset !=
PCI_CHIP_RN50_5969);
#endif
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ info->r600_shadow_fb = TRUE;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "using shadow framebuffer\n");
+ if (!xf86LoadSubModule(pScrn, "shadow"))
+ return FALSE;
+ xf86LoaderReqSymLists(shadowSymbols, NULL);
+ }
return TRUE;
}
@@ -3697,13 +3733,32 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#endif
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Initializing fb layer\n");
+
+ if (info->r600_shadow_fb) {
+ info->fb_shadow = xcalloc(1,
+ pScrn->displayWidth * pScrn->virtualY *
+ ((pScrn->bitsPerPixel + 7) >> 3));
+ if (info->fb_shadow == NULL) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Failed to allocate shadow framebuffer\n");
+ info->r600_shadow_fb = FALSE;
+ } else {
+ if (!fbScreenInit(pScreen, info->fb_shadow,
+ pScrn->virtualX, pScrn->virtualY,
+ pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
+ pScrn->bitsPerPixel))
+ return FALSE;
+ }
+ }
- /* Init fb layer */
- if (!fbScreenInit(pScreen, info->FB,
- pScrn->virtualX, pScrn->virtualY,
- pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
- pScrn->bitsPerPixel))
- return FALSE;
+ if (info->r600_shadow_fb == FALSE) {
+ /* Init fb layer */
+ if (!fbScreenInit(pScreen, info->FB,
+ pScrn->virtualX, pScrn->virtualY,
+ pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
+ pScrn->bitsPerPixel))
+ return FALSE;
+ }
xf86SetBlackWhitePixels(pScreen);
@@ -3815,6 +3870,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
RADEONChangeSurfaces(pScrn);
+
/* Enable aceleration */
if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
@@ -3883,6 +3939,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
RADEONInitVideo(pScreen);
}
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