configure.ac | 3
man/radeon.man | 6
src/Makefile.am | 3
src/atombios_crtc.c | 8
src/legacy_crtc.c | 1847 ++++++++++++++++++++++++++++++++++++++++++++++++++
src/legacy_output.c | 1732 ++++++++++++++++++++++++++++++++++++++++++++++
src/radeon.h | 41 -
src/radeon_accel.c | 337 +++++++++
src/radeon_atombios.c | 4
src/radeon_atombios.h | 11
src/radeon_bios.c | 5
src/radeon_crtc.c | 930 +------------------------
src/radeon_display.c | 878 -----------------------
src/radeon_driver.c | 1524 +----------------------------------------
src/radeon_output.c | 1275 +---------------------------------
src/radeon_tv.c | 395 ++++++++++
16 files changed, 4530 insertions(+), 4469 deletions(-)
New commits:
commit ad3325f672a241449ca239c8ee3a24b6d7703d76
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Sun Dec 23 17:18:42 2007 -0500
RADEON: Add "IgnoreLidStatus" option
Generally, users that start X with the laptop lid closed
want to use one or more external monitors rather than the
internal panel and do not want the internal panel to be on
by default. Others, it seems, want to always have the
internal panel on, regardless of the lid. I can't win.
Enable this option to force the latter.
diff --git a/man/radeon.man b/man/radeon.man
index 3c4df23..49755f4 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -467,6 +467,12 @@ Enable this option to force TV Out to always be detected
as attached.
The default is
.B off
.TP
+.BI "Option \*qIgnoreLidStatus\*q \*q" boolean \*q
+Enable this option to ignore lid status on laptops and always detect
+LVDS as attached.
+The default is
+.B off
+.TP
.SH SEE ALSO
__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__),
xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
diff --git a/src/radeon.h b/src/radeon.h
index 4a10860..d16a234 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -166,7 +166,8 @@ typedef enum {
OPTION_DEFAULT_TMDS_PLL,
OPTION_TVDAC_LOAD_DETECT,
OPTION_FORCE_TVOUT,
- OPTION_TVSTD
+ OPTION_TVSTD,
+ OPTION_IGNORE_LID_STATUS
} RADEONOpts;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 4e4f23e..6885cdc 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -219,6 +219,7 @@ static const OptionInfoRec RADEONOptions[] = {
{ OPTION_TVDAC_LOAD_DETECT, "TVDACLoadDetect", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE },
+ { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE },
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 10369d9..814c766 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -437,14 +437,18 @@ RADEONDetectLidStatus(ScrnInfoPtr pScrn)
static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn,
xf86OutputPtr output)
{
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONMonitorType MonType = MT_NONE;
if (radeon_output->type == OUTPUT_LVDS) {
+ if (xf86ReturnOptValBool(info->Options, OPTION_IGNORE_LID_STATUS,
FALSE))
+ MonType = MT_LCD;
+ else
#if defined(__powerpc__)
- MonType = MT_LCD;
+ MonType = MT_LCD;
#else
- MonType = RADEONDetectLidStatus(pScrn);
+ MonType = RADEONDetectLidStatus(pScrn);
#endif
} /*else if (radeon_output->type == OUTPUT_DVI) {
if (radeon_output->TMDSType == TMDS_INT) {
commit 20eedf348a527e1e0a5450bc22d7564895034a66
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Sun Dec 23 11:27:55 2007 -0500
RADEON: fix pll input setup on mac cards
the function was exiting before the complete setup was finished.
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 9c6c0e4..4e4f23e 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1231,19 +1231,18 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
pll->pll_out_max = 35000;
}
- if (RADEONProbePLLParameters(pScrn))
- return;
+ if (!RADEONProbePLLParameters(pScrn)) {
+ if (info->IsIGP)
+ pll->reference_freq = 1432;
+ else
+ pll->reference_freq = 2700;
- if (info->IsIGP)
- pll->reference_freq = 1432;
- else
- pll->reference_freq = 2700;
+ pll->reference_div = 12;
+ pll->xclk = 10300;
- pll->reference_div = 12;
- pll->xclk = 10300;
-
- info->sclk = 200.00;
- info->mclk = 200.00;
+ info->sclk = 200.00;
+ info->mclk = 200.00;
+ }
}
/* card limits for computing PLLs */
commit 4f2e833e8ebaba3ad85ec5314fff8fa05395b679
Author: Arkadiusz Miskiewicz <[EMAIL PROTECTED]>
Date: Fri Dec 21 18:56:34 2007 -0500
configure.ac fixes
diff --git a/configure.ac b/configure.ac
index edac3ed..409796d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -40,7 +40,7 @@ AC_PROG_LIBTOOL
AC_PROG_CC
if test "x$GCC" = "xyes"; then
- CFLAGS="$CFLAGS -Wall"
+ CPPFLAGS="$CPPFLAGS -Wall"
fi
AH_TOP([#include "xorg-server.h"])
@@ -117,6 +117,7 @@ if test "$DRI" = yes; then
fi
fi
+save_CFLAGS="$CFLAGS"
CFLAGS="$XORG_CFLAGS"
AC_CHECK_HEADER(xf86Modes.h,[XMODES=yes],[XMODES=no],[#include
"xorg-server.h"])
CFLAGS="$save_CFLAGS"
commit 2b6e8e2b8f74e94560de89693ecbc7260536591e
Author: Arkadiusz Miskiewicz <[EMAIL PROTECTED]>
Date: Fri Dec 21 18:10:17 2007 -0500
RADEON: various cleanups
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index e7ad4a9..ebfadd6 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -99,6 +99,7 @@ atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int
state)
return ATOM_NOT_IMPLEMENTED;
}
+#if 0
static void
atombios_crtc_enable(xf86CrtcPtr crtc, int enable)
{
@@ -109,6 +110,7 @@ atombios_crtc_enable(xf86CrtcPtr crtc, int enable)
//TODOavivo_wait_idle(avivo);
}
+#endif
void
atombios_crtc_dpms(xf86CrtcPtr crtc, int mode)
@@ -185,11 +187,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr
mode)
}
xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
- "crtc(%d) Clock: mode %d, PLL %u\n",
- radeon_crtc->crtc_id, mode->Clock, sclock * 10);
+ "crtc(%d) Clock: mode %d, PLL %lu\n",
+ radeon_crtc->crtc_id, mode->Clock, (long unsigned int)sclock *
10);
xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
"crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), pdiv %u\n",
- radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div);
+ radeon_crtc->crtc_id, (unsigned int)ref_div, (unsigned
int)fb_div, (unsigned int)fb_div, (unsigned int)post_div);
atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 9caebdd..694e7c7 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -847,9 +847,6 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
void
legacy_output_dpms(xf86OutputPtr output, int mode)
{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
switch(mode) {
case DPMSModeOn:
RADEONEnableDisplay(output, TRUE);
diff --git a/src/radeon.h b/src/radeon.h
index c376cdb..4a10860 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -880,6 +880,8 @@ extern void
radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg);
extern void
radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image);
+extern void
+radeon_crtc_load_lut(xf86CrtcPtr crtc);
extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr
save,
DisplayModePtr mode, xf86OutputPtr
output);
@@ -894,6 +896,10 @@ extern void RADEONInitTVRegisters(xf86OutputPtr output,
RADEONSavePtr save,
extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq, CARD32
*chosen_dot_clock_freq,
+ CARD32 *chosen_feedback_div, CARD32 *chosen_reference_div,
+ CARD32 *chosen_post_div, int flags);
+
#ifdef XF86DRI
#ifdef USE_XAA
extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a);
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index a04598d..ae32753 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1512,7 +1512,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable
(ScrnInfoPtr pScrn)
} else if (ci.sucI2cId.sbfAccess.bfI2C_LineMux) {
/* add support for GPIO line */
ErrorF("Unsupported SW GPIO - device %d: gpio line: 0x%x\n",
- i, RADEONLookupGPIOLineForDDC(pScrn,
ci.sucI2cId.sbfAccess.bfI2C_LineMux));
+ i, (unsigned int)RADEONLookupGPIOLineForDDC(pScrn,
ci.sucI2cId.sbfAccess.bfI2C_LineMux));
info->BiosConnector[i].ddc_line = 0;
} else {
info->BiosConnector[i].ddc_line = 0;
@@ -1591,7 +1591,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable
(ScrnInfoPtr pScrn)
for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
if (info->BiosConnector[i].valid) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-0x%x,
DACType-%d, TMDSType-%d, ConnectorType-%d, hpd_mask-0x%x\n",
- i, info->BiosConnector[i].ddc_line,
info->BiosConnector[i].DACType,
+ i, (unsigned int)info->BiosConnector[i].ddc_line,
info->BiosConnector[i].DACType,
info->BiosConnector[i].TMDSType,
info->BiosConnector[i].ConnectorType,
info->BiosConnector[i].hpd_mask);
}
diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h
index 33925a5..bfac93e 100644
--- a/src/radeon_atombios.h
+++ b/src/radeon_atombios.h
@@ -110,6 +110,17 @@ extern AtomBiosResult
RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle,
AtomBiosRequestID id, AtomBiosArgPtr data);
+extern Bool
+RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn);
+extern Bool
+RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn);
+
+extern int
+atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode);
+
+extern void
+atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int
*major, int *minor);
+
# include "xf86int10.h"
# ifdef ATOM_BIOS_PARSER
# define INT8 INT8
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 1a4f99d..9253182 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -305,7 +305,7 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr
pScrn)
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-0x%x,
DACType-%d, TMDSType-%d, ConnectorType-%d\n",
- i, info->BiosConnector[i].ddc_line,
info->BiosConnector[i].DACType,
+ i, (unsigned int)info->BiosConnector[i].ddc_line,
info->BiosConnector[i].DACType,
info->BiosConnector[i].TMDSType,
info->BiosConnector[i].ConnectorType);
}
}
@@ -494,7 +494,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS
(ScrnInfoPtr pScrn)
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-0x%x,
DACType-%d, TMDSType-%d, ConnectorType-%d\n",
- i, info->BiosConnector[i].ddc_line,
info->BiosConnector[i].DACType,
+ i, (unsigned int)info->BiosConnector[i].ddc_line,
info->BiosConnector[i].DACType,
info->BiosConnector[i].TMDSType,
info->BiosConnector[i].ConnectorType);
}
}
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 9034cf5..2f9034a 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -86,9 +86,6 @@ radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
static void
radeon_crtc_mode_prepare(xf86CrtcPtr crtc)
{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
radeon_crtc_dpms(crtc, DPMSModeOff);
}
@@ -178,10 +175,10 @@ RADEONComputePLL(RADEONPLLPtr pll,
}
}
- ErrorF("best_freq: %u\n", best_freq);
- ErrorF("best_feedback_div: %u\n", best_feedback_div);
- ErrorF("best_ref_div: %u\n", best_ref_div);
- ErrorF("best_post_div: %u\n", best_post_div);
+ ErrorF("best_freq: %u\n", (unsigned int)best_freq);
+ ErrorF("best_feedback_div: %u\n", (unsigned int)best_feedback_div);
+ ErrorF("best_ref_div: %u\n", (unsigned int)best_ref_div);
+ ErrorF("best_post_div: %u\n", (unsigned int)best_post_div);
*chosen_dot_clock_freq = best_freq / 10000;
*chosen_feedback_div = best_feedback_div;
@@ -207,9 +204,6 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
static void
radeon_crtc_mode_commit(xf86CrtcPtr crtc)
{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
radeon_crtc_dpms(crtc, DPMSModeOn);
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index b9a05f3..9c6c0e4 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -144,6 +144,8 @@ extern void
RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
extern void
RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void
+RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
#ifdef USE_XAA
#ifdef XF86DRI
@@ -1191,7 +1193,6 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONPLLPtr pll = &info->pll;
double min_dotclock;
@@ -1468,7 +1469,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
if (info->ChipFamily >= CHIP_FAMILY_R600) {
info->mc_fb_location = (aper0_base >> 24) |
(((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
- ErrorF("mc fb loc is %08x\n", info->mc_fb_location);
+ ErrorF("mc fb loc is %08x\n", (unsigned
int)info->mc_fb_location);
} else {
info->mc_fb_location = (aper0_base >> 16) |
((aper0_base + mem_size - 1) & 0xffff0000U);
@@ -2607,10 +2608,8 @@ static void RADEONPreInitBIOS(ScrnInfoPtr pScrn,
xf86Int10InfoPtr pInt10)
static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn)
{
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONInfoPtr info = RADEONPTR(pScrn);
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
- int i;
if (info->IsPrimary) {
xf86OutputDestroy(config->output[0]);
@@ -2627,7 +2626,6 @@ static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn)
static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn)
{
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONInfoPtr info = RADEONPTR(pScrn);
int i;
int mask;
@@ -3672,7 +3670,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
"RADEONRestoreMemMapRegisters() : \n");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
" MC_FB_LOCATION : 0x%08x 0x%08x\n",
- (unsigned)restore->mc_fb_location, mc_fb_loc);
+ (unsigned)restore->mc_fb_location, (unsigned int)mc_fb_loc);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
" MC_AGP_LOCATION : 0x%08x\n",
(unsigned)restore->mc_agp_location);
@@ -3789,7 +3787,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
"Timeout trying to update memory controller
settings !\n");
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"MC_STATUS = 0x%08x (on entry = 0x%08x)\n",
- INREG(RADEON_MC_STATUS), (unsigned
int)old_mc_status);
+ (unsigned int)INREG(RADEON_MC_STATUS), (unsigned
int)old_mc_status);
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"You will probably crash now ... \n");
/* Nothing we can do except maybe try to kill the server,
@@ -3891,10 +3889,10 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr
pScrn, RADEONSavePtr save)
"DRI init changed memory map, adjusting ...\n");
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
" MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n",
- info->mc_fb_location, fb);
+ (long unsigned int)info->mc_fb_location, (long unsigned
int)fb);
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
" MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
- info->mc_agp_location, agp);
+ (long unsigned int)info->mc_agp_location, (long unsigned
int)agp);
info->mc_fb_location = fb;
info->mc_agp_location = agp;
if (info->ChipFamily >= CHIP_FAMILY_R600)
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 84b1dd9..10369d9 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -198,7 +198,7 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn)
ConnectorTypeName[radeon_output->ConnectorType],
DACTypeName[radeon_output->DACType+1],
TMDSTypeName[radeon_output->TMDSType+1],
- radeon_output->ddc_line);
+ (unsigned int)radeon_output->ddc_line);
}
}
@@ -232,7 +232,7 @@ avivo_display_ddc_connected(ScrnInfoPtr pScrn,
xf86OutputPtr output)
} else MonType = MT_NONE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "DDC Type: 0x%x, Detected Monitor Type: %d\n",
radeon_output->ddc_line, MonType);
+ "DDC Type: 0x%x, Detected Monitor Type: %d\n", (unsigned
int)radeon_output->ddc_line, MonType);
return MonType;
}
@@ -332,7 +332,7 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr
output)
} else MonType = MT_NONE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "DDC Type: 0x%x, Detected Monitor Type: %d\n",
radeon_output->ddc_line, MonType);
+ "DDC Type: 0x%x, Detected Monitor Type: %d\n", (unsigned
int)radeon_output->ddc_line, MonType);
return MonType;
}
@@ -1196,6 +1196,7 @@ void RADEONSetOutputType(ScrnInfoPtr pScrn,
RADEONOutputPrivatePtr radeon_output
radeon_output->type = output;
}
+#if 0
static
Bool AVIVOI2CReset(ScrnInfoPtr pScrn)
{
@@ -1207,6 +1208,7 @@ Bool AVIVOI2CReset(ScrnInfoPtr pScrn)
OUTREG(AVIVO_I2C_STOP, 0x0);
return TRUE;
}
+#endif
static
Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state, int gpio_reg)
@@ -1669,7 +1671,7 @@ void RADEONInitConnector(xf86OutputPtr output)
RADEONOutputPrivatePtr radeon_output = output->driver_private;
char stmp[16];
char *name;
- sprintf(stmp, "DDC_0x%x", radeon_output->ddc_line);
+ sprintf(stmp, "DDC_0x%x", (unsigned int)radeon_output->ddc_line);
name = xnfalloc(strlen(stmp) + 1);
strcpy(name, stmp);
@@ -2224,11 +2226,11 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].valid = TRUE;
info->BiosConnector[1].valid = TRUE;
if (sscanf(optstr, "%u,%d,%d,%u,%u,%d,%d,%u",
- &info->BiosConnector[0].ddc_line,
+ (unsigned int *)&info->BiosConnector[0].ddc_line,
&info->BiosConnector[0].DACType,
&info->BiosConnector[0].TMDSType,
&info->BiosConnector[0].ConnectorType,
- &info->BiosConnector[1].ddc_line,
+ (unsigned int *)&info->BiosConnector[1].ddc_line,
&info->BiosConnector[1].DACType,
&info->BiosConnector[1].TMDSType,
&info->BiosConnector[1].ConnectorType) != 8) {
commit 4c6f60e3b19ac55ab1255c79df03b1df5950864e
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Fri Dec 21 17:33:04 2007 -0500
RADEON: clean up prototypes
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 799aa2e..9caebdd 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -212,7 +212,6 @@ RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
}
}
-
Bool
RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch)
{
diff --git a/src/radeon.h b/src/radeon.h
index 5c15888..c376cdb 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -849,22 +849,15 @@ extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn);
extern void RADEONUnblank(ScrnInfoPtr pScrn);
extern void RADEONUnblank(ScrnInfoPtr pScrn);
extern void RADEONBlank(ScrnInfoPtr pScrn);
-extern void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
- int PowerManagementMode,
- int flags);
+
extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
extern Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn);
-extern int RADEONValidateMergeModes(ScrnInfoPtr pScrn);
-extern int RADEONValidateDDCModes(ScrnInfoPtr pScrn1, char **ppModeName,
- RADEONMonitorType DisplayType, int crtc2);
+
extern void RADEONSetPitch (ScrnInfoPtr pScrn);
extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode);
-DisplayModePtr
+extern DisplayModePtr
RADEONProbeOutputModes(xf86OutputPtr output);
-extern Bool RADEONInit2(ScrnInfoPtr pScrn, DisplayModePtr crtc1,
- DisplayModePtr crtc2, int crtc_mask,
- RADEONSavePtr save, RADEONMonitorType montype);
extern Bool
RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch);
@@ -875,20 +868,18 @@ RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output);
extern Bool
RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output);
-void
+extern void
radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y);
-void
+extern void
radeon_crtc_show_cursor (xf86CrtcPtr crtc);
-void
+extern void
radeon_crtc_hide_cursor (xf86CrtcPtr crtc);
-void
+extern void
radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y);
-void
+extern void
radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg);
-void
+extern void
radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image);
-void
-RADEONEnableOutputs(ScrnInfoPtr pScrn, int crtc_num);
extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr
save,
DisplayModePtr mode, xf86OutputPtr
output);
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 752b31e..1a4f99d 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -65,6 +65,7 @@ typedef enum
CONNECTOR_UNSUPPORTED_LEGACY
} RADEONLegacyConnectorType;
+
/* Read the Video BIOS block and the FP registers (if applicable). */
Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
{
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 1662e04..b9a05f3 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -128,6 +128,31 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn,
RADEONSavePtr save);
extern DisplayModePtr
RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode);
+extern void
+RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void
+RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void
+RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void
+RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void
+RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void
+RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void
+RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void
+RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+
+#ifdef USE_XAA
+#ifdef XF86DRI
+extern Bool
+RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen);
+#endif /* XF86DRI */
+extern Bool
+RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen);
+#endif /* USE_XAA */
static const OptionInfoRec RADEONOptions[] = {
{ OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE },
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 2346932..84b1dd9 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -177,6 +177,7 @@ extern void legacy_output_dpms(xf86OutputPtr output, int
mode);
extern RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr
output);
extern RADEONMonitorType legacy_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr
output);
extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr
mode);
+extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr);
void RADEONPrintPortMap(ScrnInfoPtr pScrn)
commit 8c761afdcb9baf1649b93449692fb9ab67bc2c80
Author: Alex Deucher <[EMAIL PROTECTED](none)>
Date: Fri Dec 21 16:24:49 2007 -0500
RADEON: more re-org
move save/restore routines into legacy_crtc/output
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index f1bf9be..4a7071a 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -53,6 +53,585 @@
#include "sarea.h"
#endif
+/* Write common registers */
+void
+RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ if (info->IsSecondary)
+ return;
+
+ OUTREG(RADEON_OVR_CLR, restore->ovr_clr);
+ OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
+ OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
+ OUTREG(RADEON_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
+ OUTREG(RADEON_SUBPIC_CNTL, restore->subpic_cntl);
+ OUTREG(RADEON_VIPH_CONTROL, restore->viph_control);
+ OUTREG(RADEON_I2C_CNTL_1, restore->i2c_cntl_1);
+ OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl);
+ OUTREG(RADEON_CAP0_TRIG_CNTL, restore->cap0_trig_cntl);
+ OUTREG(RADEON_CAP1_TRIG_CNTL, restore->cap1_trig_cntl);
+ OUTREG(RADEON_BUS_CNTL, restore->bus_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl);
+
+ /* Workaround for the VT switching problem in dual-head mode. This
+ * problem only occurs on RV style chips, typically when a FP and
+ * CRT are connected.
+ */
+ if (pRADEONEnt->HasCRTC2 &&
+ info->ChipFamily != CHIP_FAMILY_R200 &&
+ !IS_R300_VARIANT) {
+ CARD32 tmp;
+
+ tmp = INREG(RADEON_DAC_CNTL2);
+ OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL);
+ usleep(100000);
+ }
+}
+
+
+/* Write CRTC registers */
+void
+RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Programming CRTC1, offset: 0x%08x\n",
+ (unsigned)restore->crtc_offset);
+
+ /* We prevent the CRTC from hitting the memory controller until
+ * fully programmed
+ */
+ OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl |
+ RADEON_CRTC_DISP_REQ_EN_B);
+
+ OUTREGP(RADEON_CRTC_EXT_CNTL,
+ restore->crtc_ext_cntl,
+ RADEON_CRTC_VSYNC_DIS |
+ RADEON_CRTC_HSYNC_DIS |
+ RADEON_CRTC_DISPLAY_DIS);
+
+ OUTREG(RADEON_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
+ OUTREG(RADEON_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
+ OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
+ OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
+
+ OUTREG(RADEON_FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid);
+ OUTREG(RADEON_FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid);
+ OUTREG(RADEON_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
+ OUTREG(RADEON_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
+
+ if (IS_R300_VARIANT)
+ OUTREG(R300_CRTC_TILE_X0_Y0, restore->crtc_tile_x0_y0);
+ OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
+ OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset);
+
+ OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch);
+ OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl);
+ OUTREG(RADEON_CRTC_MORE_CNTL, restore->crtc_more_cntl);
+
+ if (info->IsDellServer) {
+ OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
+ OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
+ OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
+ OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
+ }
+
+ OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
+}
+
+/* Write CRTC2 registers */
+void
+RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ /* CARD32 crtc2_gen_cntl;*/
+
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Programming CRTC2, offset: 0x%08x\n",
+ (unsigned)restore->crtc2_offset);
+
+ /* We prevent the CRTC from hitting the memory controller until
+ * fully programmed
+ */
+ OUTREG(RADEON_CRTC2_GEN_CNTL,
+ restore->crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
+ RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS |
+ RADEON_CRTC2_DISP_REQ_EN_B);
+
+ OUTREG(RADEON_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp);
+ OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
+ OUTREG(RADEON_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp);
+ OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid);
+
+ OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp_h2_sync_strt_wid);
+ OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp_v2_sync_strt_wid);
+
+ if (IS_R300_VARIANT)
+ OUTREG(R300_CRTC2_TILE_X0_Y0, restore->crtc2_tile_x0_y0);
+ OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
+ OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset);
+
+ OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch);
+ OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
+
+ if (info->ChipFamily == CHIP_FAMILY_RS400) {
+ OUTREG(RADEON_RS480_UNK_e30, restore->rs480_unk_e30);
+ OUTREG(RADEON_RS480_UNK_e34, restore->rs480_unk_e34);
+ OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38);
+ OUTREG(RADEON_RS480_UNK_e3c, restore->rs480_unk_e3c);
+ }
+ OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
+
+}
+
+static void
+RADEONPLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn)
+{
+ int i = 0;
+
+ /* FIXME: Certain revisions of R300 can't recover here. Not sure of
+ the cause yet, but this workaround will mask the problem for now.
+ Other chips usually will pass at the very first test, so the
+ workaround shouldn't have any effect on them. */
+ for (i = 0;
+ (i < 10000 &&
+ INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
+ i++);
+}
+
+static void
+RADEONPLLWriteUpdate(ScrnInfoPtr pScrn)
+{
+ while (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
+
+ OUTPLLP(pScrn, RADEON_PPLL_REF_DIV,
+ RADEON_PPLL_ATOMIC_UPDATE_W,
+ ~(RADEON_PPLL_ATOMIC_UPDATE_W));
+}
+
+static void
+RADEONPLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn)
+{
+ int i = 0;
+
+ /* FIXME: Certain revisions of R300 can't recover here. Not sure of
+ the cause yet, but this workaround will mask the problem for now.
+ Other chips usually will pass at the very first test, so the
+ workaround shouldn't have any effect on them. */
+ for (i = 0;
+ (i < 10000 &&
+ INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
+ i++);
+}
+
+static void
+RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn)
+{
+ while (INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
+
+ OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV,
+ RADEON_P2PLL_ATOMIC_UPDATE_W,
+ ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
+}
+
+static CARD8
+RADEONComputePLLGain(CARD16 reference_freq, CARD16 ref_div,
+ CARD16 fb_div)
+{
+ unsigned vcoFreq;
+
+ if (!ref_div)
+ return 1;
+
+ vcoFreq = ((unsigned)reference_freq * fb_div) / ref_div;
+
+ /*
+ * This is horribly crude: the VCO frequency range is divided into
+ * 3 parts, each part having a fixed PLL gain value.
+ */
+ if (vcoFreq >= 30000)
+ /*
+ * [300..max] MHz : 7
+ */
+ return 7;
+ else if (vcoFreq >= 18000)
+ /*
+ * [180..300) MHz : 4
+ */
+ return 4;
+ else
+ /*
+ * [0..180) MHz : 1
+ */
+ return 1;
+}
+
+/* Write PLL registers */
+void
+RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ CARD8 pllGain;
+
+#if defined(__powerpc__)
+ /* apparently restoring the pll causes a hang??? */
+ if (info->MacModel == RADEON_MAC_IBOOK)
+ return;
+#endif
+
+ pllGain = RADEONComputePLLGain(info->pll.reference_freq,
+ restore->ppll_ref_div &
RADEON_PPLL_REF_DIV_MASK,
+ restore->ppll_div_3 &
RADEON_PPLL_FB3_DIV_MASK);
+
+ if (info->IsMobility) {
+ /* A temporal workaround for the occational blanking on certain laptop
panels.
+ This appears to related to the PLL divider registers (fail to
lock?).
+ It occurs even when all dividers are the same with their old
settings.
+ In this case we really don't need to fiddle with PLL registers.
+ By doing this we can avoid the blanking problem with some panels.
+ */
+ if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) &
RADEON_PPLL_REF_DIV_MASK)) &&
+ (restore->ppll_div_3 == (INPLL(pScrn, RADEON_PPLL_DIV_3) &
+ (RADEON_PPLL_POST3_DIV_MASK |
RADEON_PPLL_FB3_DIV_MASK)))) {
+ OUTREGP(RADEON_CLOCK_CNTL_INDEX,
+ RADEON_PLL_DIV_SEL,
+ ~(RADEON_PLL_DIV_SEL));
+ RADEONPllErrataAfterIndex(info);
+ return;
+ }
+ }
+
+ OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL,
+ RADEON_VCLK_SRC_SEL_CPUCLK,
+ ~(RADEON_VCLK_SRC_SEL_MASK));
+
+ OUTPLLP(pScrn,
+ RADEON_PPLL_CNTL,
+ RADEON_PPLL_RESET
+ | RADEON_PPLL_ATOMIC_UPDATE_EN
+ | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
+ | ((CARD32)pllGain << RADEON_PPLL_PVG_SHIFT),
+ ~(RADEON_PPLL_RESET
+ | RADEON_PPLL_ATOMIC_UPDATE_EN
+ | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
+ | RADEON_PPLL_PVG_MASK));
+
+ OUTREGP(RADEON_CLOCK_CNTL_INDEX,
+ RADEON_PLL_DIV_SEL,
+ ~(RADEON_PLL_DIV_SEL));
+ RADEONPllErrataAfterIndex(info);
+
+ if (IS_R300_VARIANT ||
+ (info->ChipFamily == CHIP_FAMILY_RS300) ||
+ (info->ChipFamily == CHIP_FAMILY_RS400)) {
+ if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
+ /* When restoring console mode, use saved PPLL_REF_DIV
+ * setting.
+ */
+ OUTPLLP(pScrn, RADEON_PPLL_REF_DIV,
+ restore->ppll_ref_div,
+ 0);
+ } else {
+ /* R300 uses ref_div_acc field as real ref divider */
+ OUTPLLP(pScrn, RADEON_PPLL_REF_DIV,
+ (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
+ ~R300_PPLL_REF_DIV_ACC_MASK);
+ }
+ } else {
+ OUTPLLP(pScrn, RADEON_PPLL_REF_DIV,
+ restore->ppll_ref_div,
+ ~RADEON_PPLL_REF_DIV_MASK);
+ }
+
+ OUTPLLP(pScrn, RADEON_PPLL_DIV_3,
+ restore->ppll_div_3,
+ ~RADEON_PPLL_FB3_DIV_MASK);
+
+ OUTPLLP(pScrn, RADEON_PPLL_DIV_3,
+ restore->ppll_div_3,
+ ~RADEON_PPLL_POST3_DIV_MASK);
+
+ RADEONPLLWriteUpdate(pScrn);
+ RADEONPLLWaitForReadUpdateComplete(pScrn);
+
+ OUTPLL(pScrn, RADEON_HTOTAL_CNTL, restore->htotal_cntl);
+
+ OUTPLLP(pScrn, RADEON_PPLL_CNTL,
+ 0,
+ ~(RADEON_PPLL_RESET
+ | RADEON_PPLL_SLEEP
+ | RADEON_PPLL_ATOMIC_UPDATE_EN
+ | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
+
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
+ restore->ppll_ref_div,
+ restore->ppll_div_3,
+ (unsigned)restore->htotal_cntl,
+ INPLL(pScrn, RADEON_PPLL_CNTL));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "Wrote: rd=%d, fd=%d, pd=%d\n",
+ restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
+ restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
+ (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
+
+ usleep(50000); /* Let the clock to lock */
+
+ OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL,
+ RADEON_VCLK_SRC_SEL_PPLLCLK,
+ ~(RADEON_VCLK_SRC_SEL_MASK));
+
+ /*OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl);*/
--
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