On Thu, 21 May 2026 08:24:31 GMT, Andrew Haley <[email protected]> wrote:
>> src/hotspot/cpu/aarch64/assembler_aarch64.hpp line 3166:
>>
>>> 3164: assert(Ts == H ? Vm->encoding() < 16 : Vm->encoding() < 32,
>>> "umull{2}v requires Vm to be in range V0..V15 when Ts is H");
>>> 3165: f(0, 31), f(q, 30), f(0b101111, 29, 24), f(size, 23, 22), f(l,
>>> 21); //f(m, 20);
>>> 3166: rf(Vm, 16), f(0b1010, 15, 12), f(h, 11), f(0, 10), rf(Vn, 5),
>>> rf(Vd, 0);
>>
>> Why `f(m, 20)` is commented here? Does it need to be set?
>
> It doesn't. AArch64 assembler throws an assertion if any field of an
> instruction is not set. I think it's because `Vm` may have to be <15, so that
> bi twill be clear. But the comment is more confusing than helpful.
Still confused on correctness here, bear with me for a sec.
So current code means we set bit 20 implicitly to `0`, when `Ts == H`, because
it implies `Vm < 16`. But with `H` variant, don't we need to encode lane bits
as H:L:M explicitly? Meaning, `M` is the lower bit of the lane, shouldn't it be
dependent on `lane`, rather than being always `0`?
Actually, a few lines above, when `size == 0b01`, we do not take the lower bit
out of `lane` at all? That's our `M`?
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PR Review Comment: https://git.openjdk.org/jdk/pull/30941#discussion_r3279810188
