xiaoxiang781216 commented on a change in pull request #5148:
URL: https://github.com/apache/incubator-nuttx/pull/5148#discussion_r777803567
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File path: arch/risc-v/src/common/riscv_assert.c
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@@ -98,35 +106,35 @@ static inline void riscv_registerdump(volatile uintptr_t
*regs)
{
/* Are user registers available from interrupt processing? */
- _alert("EPC:%016" PRIx64 "\n", regs[REG_EPC]);
- _alert("A0:%016" PRIx64 " A1:%01" PRIx64 "6 A2:%016" PRIx64
- " A3:%016" PRIx64 "\n",
+ _alert("EPC:%0" PRIxREG "\n", regs[REG_EPC]);
+ _alert("A0:%0" PRIxREG " A1:%0" PRIxREG "A2:%0" PRIxREG
+ " A3:%0" PRIxREG "\n",
regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3]);
- _alert("A4:%016" PRIx64 " A5:%016" PRIx64 "A6:%016" PRIx64
- " A7:%016" PRIx64 "\n",
+ _alert("A4:%0" PRIxREG " A5:%0" PRIxREG "A6:%0" PRIxREG
Review comment:
let's move %0 into PRIxREG?
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