pcwang-thead added a comment.
Thanks! I think it's a great improvement!
================
Comment at: llvm/lib/Target/RISCV/RISCV.td:509
-def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>;
-def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
+class RISCVProcessorModelPROC<string enum, string enum_features, string
default_march> {
+ string Enum = enum;
----------------
Can `EnumFeatures/DefaultMarch` string be inferred from ProcessorModel's
SubtargetFeature if not specified and `Enum` just be the uppercase of the name
of ProcessorModel? The implementation could be more complicated but I think
it's worthy.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137517/new/
https://reviews.llvm.org/D137517
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