On 03/02/2017 19:43, "Tony Duell" <ard.p850...@gmail.com> wrote:
> But that's why I said 'about'. I am doing order-of-magnitude calculations, > not trying to design a delay line. I would estimate that between adjacent > ICs on the same board you'd get a delay measured in 10's or 100's of > picoseconds. That sort of order. So a 25MHz logic analyser, with an > effective time resolution of 40ns (if that) is not going to show it. > > There is no way you're going to get delays of 40ns between adjacent > ICs on any reasonable PCB. This is the sort of thing I mean: http://www.binarydinosaurs.co.uk/STCExecutelA1checking.jpg Watching the A1 address line (no triggers just sampling 6 points) and a pulse appears at ROM4 on the falling edge of the ALE signal but not the other 3 ROMs or the LS373 flip-flop that's demultiplexing the AD1 pin of the 8085. While I was thinking about the possibility of propagation delay I noticed this one: http://www.binarydinosaurs.co.uk/STCExecutelA1checking2.jpg Pulse missing from ROM3. Given the paths on this board aren't massive and resistance is equal between all points when measured with a DMM (and all sockets have been replaced, traces checked etc) what else could I be looking at? -- Adrian/Witchy Binary Dinosaurs creator/curator Www.binarydinosaurs.co.uk - the UK's biggest private home computer collection?
