On 12/17/2016 05:50 PM, Eric Smith wrote: > > The TI TMS34010 and TMS34020 graphics processors were > bit-addressable, though instructions had to be 16-bit aligned. The > TMS34010 and the default mode of the TMS34020 were little-endian, > with bit 0 being the least significant bit. The TMS34020 has > configurable support for big-endian memory addressing.
I'd forgotten about the TIGA chips, thanks. --Chuck
