On Tue, 24 Sep 2024 03:45:32 GMT, Fei Yang <fy...@openjdk.org> wrote:
>> Hamlin Li has updated the pull request incrementally with one additional >> commit since the last revision: >> >> refine comment > > src/hotspot/cpu/riscv/assembler_riscv.hpp line 51: > >> 49: n_int_register_parameters_c = 8, // x10, x11, ... x17 (c_rarg0, >> c_rarg1, ...) >> 50: n_float_register_parameters_c = 8, // f10, f11, ... f17 (c_farg0, >> c_farg1, ... ) >> 51: n_vector_register_parameters_c = 8, // v8, v9, ... v15 > > I know vector registers are not used for passing arguments or return values > by the RISCV ABI for now. But I guess it might be better and consistent to > align with the numbering of integer and floating-point argument registers > (x10 - x17, f10 - f17)? That is v10 - v17. Note in the RISC-V ELF psABI there is a convetion variant for v-regs. If you add function attribute riscv_vector_cc it should be used for C/C++. (I never tested it) v0 = first vector mask argument v8-v23 = args/rets v1-v7/v24-v31 = caller saved https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc ------------- PR Review Comment: https://git.openjdk.org/jdk/pull/21083#discussion_r1772630985
