On Fri, Dec 27, 2024 at 01:24:40PM -0800, Paul Lalonde wrote: > The remnants of that work are now living on in the AVX512 instruction set. > The principal problem with Larrabee was that the ring bus connecting some > 60+ ring stops was *so wide* (512 bits bidirectional = 1024 bits!) that it > consumed too much power. It was more flexible than it needed to be > compared to a GPU memory controller/crossbar, and its power consumption > couldn't be reduced sufficiently to make it a useful architecture for the > mobile market. Instead, graphics continued on the older Intel embedded > graphics path.
Is the power consumption the reason the cores downclock when you start sending AVX512 instructions? By far the most useful results of our yaers-long Phi experiment was being able to test tons of codes to see which ones benefit from AVX512 and which ones wind up being penalized so badly by clock reduction that they weren't worth porting. It set us up to be able to deploy efficiently in the followon generations of x86_64. We never came to a conclusion whether it was power consumption or heat that required the slowdown. I guess it could be both. > Frankly, I'm amazed that Intel followed through with 2 more revisions of > Xeon Phi before canning it. So were we. The 5110 chips were plagued with reliability problems, and the software stack was ... tough to get support for. The host-cpu Knights Landing systems were much more pleasant to work with, but we hadn't finished benchmarking them by the time Intil pulled the plug. khm ------------------------------------------ 9fans: 9fans Permalink: https://9fans.topicbox.com/groups/9fans/T7692a612f26c8ec5-M3198d5ce755d47ebe87068a2 Delivery options: https://9fans.topicbox.com/groups/9fans/subscription
